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51. 发明申请

US20110266034A1 Preventing breakage of long metal signal conductors on semiconductor substrates 有权
标题翻译：防止半导体基板上的长金属信号导体断裂
公开(公告)号：US20110266034A1
公开(公告)日：2011-11-03
申请号：US13135510
申请日：2011-07-07
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H05K1/02 , H01L21/28
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： An apparatus includes a volume of insulator disposed over a top surface of a semiconductor substrate, a tube of soft dielectric, and a metal conductor. The insulator has a hardness of more than approximately three gigaPascals (gPa) and the soft dielectric has a hardness of less than three gPa. The tube of soft dielectric and the metal conductor are both embedded within the volume of insulator. The tube defines a central volume and the metal conductor extends in a direction through the central volume for a distance of at least one inch. The metal conductor is encircled by the soft dielectric when the apparatus is viewed in a cross-sectional plane perpendicular to the direction. The metal conductor may include a plurality of bend portions. The metal conductor does not break when the apparatus is temperature cycled over a range from zero to eighty five degrees Celsius.
摘要翻译：一种装置包括设置在半导体衬底的顶表面上的绝缘体体积，软电介质管和金属导体。绝缘体具有大于约3千兆帕（gPa）的硬度，软电介质具有小于3gPa的硬度。软电介质管和金属导体都嵌入在绝缘体的体积内。管限定中心体积，并且金属导体沿着穿过中心体积的方向延伸至少一英寸的距离。当在垂直于该方向的横截面中观察装置时，金属导体被软电介质环绕。金属导体可以包括多个弯曲部分。当设备在零度至摄氏度摄氏八十度的范围内温度循环时，金属导体不会断裂。

52. 发明授权

US07978029B2 Multiple-layer signal conductor 有权
标题翻译：多层信号导体
公开(公告)号：US07978029B2
公开(公告)日：2011-07-12
申请号：US12387873
申请日：2009-05-09
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01P3/08
CPC分类号： H01P3/08
摘要： A multiple-layer signal conductor has increased surface area for mitigation of skin effect. Parallel extending elongated strips of conductive material are placed in parallel layers and are separated by a thin layer of dielectric. The elongated strips are conductively connected to one another by regularly spaced vias such that a single signal conductor with multiple conductive layers is formed. During high-speed signaling, the skin effect causes current to concentrate near the surfaces of conductors. The multiple-layer signal conductor, however, has increased surface area with respect to its total cross-sectional area. The effective cross-sectional area which is conductive during high-speed signaling is therefore increased, leading to positive effects on transmission line resistance, heating, signal integrity and signal propagation delay. The multiple-layer signal conductor sees special use on silicon circuit boards and can conduct signals at ten gigahertz or greater for distances of up to five inches without rebuffering or termination.
摘要翻译：多层信号导体具有增加的表面积，以减轻皮肤效应。平行延伸的细长导电材料条被放置成平行的层并且被薄的电介质隔开。细长带通过规则间隔的通孔彼此导电连接，从而形成具有多个导电层的单个信号导体。在高速信号传递期间，皮肤效应导致电流集中在导体表面附近。然而，多层信号导体相对于其总横截面面积增加了表面积。因此，在高速信号传导期间导通的有效截面面积增加，导致对传输线电阻，加热，信号完整性和信号传播延迟的积极影响。多层信号导体在硅电路板上特别使用，并且可以以10千兆赫或更大的距离传输高达五英寸的距离，而无需重新制止或终止。

53. 发明授权

US07764498B2 Comb-shaped power bus bar assembly structure having integrated capacitors 有权
标题翻译：具有集成电容器的梳状电力母线组件结构
公开(公告)号：US07764498B2
公开(公告)日：2010-07-27
申请号：US11975011
申请日：2007-10-16
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H05K7/20
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： A reconfigurable high performance computer occupies less than 360 cubic inches and has an approximate compute power of 0.7 teraflops per second while consuming less than 1000 watts. The computer includes a novel stack of semiconductor substrate assemblies. Some semiconductor substrate assemblies involve field programmable gate array (FPGA) dice that are directly surface mounted, as bare die, to a semiconductor substrate. Other semiconductor substrate assemblies of the stack involve bare memory integrated circuit dice that are directly surface mounted to a semiconductor substrate. Elastomeric connectors interconnect adjacent semiconductor substrates proceeding down the stack. Tines of novel comb-shaped power bus bar assembly structures extend into the stack to supply DC supply voltages. The supply voltages are supplied from bus bars, through vias in the semiconductor substrates, and to the integrated circuits on the other side of the substrates. The power bus bars also serve as capacitors and guides for liquid coolant.
摘要翻译：可重新配置的高性能计算机占用小于360立方英寸，并且具有每秒0.7 teraflops的近似计算能力，同时消耗少于1000瓦特。该计算机包括一组新的半导体衬底组件。一些半导体衬底组件涉及作为裸芯片直接表面安装到半导体衬底的现场可编程门阵列（FPGA）裸片。堆叠的其他半导体衬底组件包括直接表面安装到半导体衬底的裸存储器集成电路裸片。弹性连接器将相邻的半导体衬底互相连接，沿堆叠进入。新颖的梳状电源母线组合结构的齿条延伸到堆叠中以提供直流电源电压。电源电压由母线，半导体衬底中的通孔以及衬底另一侧的集成电路提供。电力母线还用作液体冷却剂的电容器和导轨。

54. 发明申请

US20090080158A1 Comb-shaped power bus bar assembly structure having integrated capacitors 有权
标题翻译：具有集成电容器的梳状电力母线组件结构
公开(公告)号：US20090080158A1
公开(公告)日：2009-03-26
申请号：US11975011
申请日：2007-10-16
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H05K7/20 , G06F1/20 , H02G5/00 , H05K1/18
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： A reconfigurable high performance computer occupies less than 360 cubic inches and has an approximate compute power of 0.7 teraflops per second while consuming less than 1000 watts. The computer includes a novel stack of semiconductor substrate assemblies. Some semiconductor substrate assemblies involve field programmable gate array (FPGA) dice that are directly surface mounted, as bare die, to a semiconductor substrate. Other semiconductor substrate assemblies of the stack involve bare memory integrated circuit dice that are directly surface mounted to a semiconductor substrate. Elastomeric connectors interconnect adjacent semiconductor substrates proceeding down the stack. Tines of novel comb-shaped power bus bar assembly structures extend into the stack to supply DC supply voltages. The supply voltages are supplied from bus bars, through vias in the semiconductor substrates, and to the integrated circuits on the other side of the substrates. The power bus bars also serve as capacitors and guides for liquid coolant.
摘要翻译：可重新配置的高性能计算机占用小于360立方英寸，并且具有每秒0.7 teraflops的近似计算能力，同时消耗少于1000瓦特。该计算机包括一组新的半导体衬底组件。一些半导体衬底组件涉及作为裸芯片直接表面安装到半导体衬底的现场可编程门阵列（FPGA）裸片。堆叠的其他半导体衬底组件包括直接表面安装到半导体衬底的裸存储器集成电路裸片。弹性连接器将相邻的半导体衬底互相连接，沿堆叠进入。新颖的梳状电源母线组合结构的齿条延伸到堆叠中以提供直流电源电压。电源电压由母线，半导体衬底中的通孔以及衬底另一侧的集成电路提供。电力母线还用作液体冷却剂的电容器和导轨。

55. 发明申请

US20090079084A1 Preventing breakage of long metal signal conductors on semiconductor substrates 有权
标题翻译：防止半导体基板上的长金属信号导体断裂
公开(公告)号：US20090079084A1
公开(公告)日：2009-03-26
申请号：US11975058
申请日：2007-10-16
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： An apparatus includes a volume of insulator disposed over a top surface of a semiconductor substrate, a tube of soft dielectric, and a metal conductor. The insulator has a hardness of more than approximately three gigapascals (gPa) and the soft dielectric has a hardness of less than three gPa. The tube of soft dielectric and the metal conductor are both embedded within the volume of insulator. The tube defines a central volume and the metal conductor extends in a direction through the central volume for a distance of at least one inch. The metal conductor is encircled by the soft dielectric when the apparatus is viewed in a cross-sectional plane perpendicular to the direction. The metal conductor may include a plurality of bend portions. The metal conductor does not break when the apparatus is temperature cycled over a range from zero to eighty five degrees Celsius.
摘要翻译：一种装置包括设置在半导体衬底的顶表面上的绝缘体体积，软电介质管和金属导体。绝缘体的硬度大于约3吉帕斯卡（gPa），软电介质具有小于3gPa的硬度。软电介质管和金属导体都嵌入在绝缘体的体积内。管限定中心体积，并且金属导体沿着穿过中心体积的方向延伸至少一英寸的距离。当在垂直于该方向的横截面中观察装置时，金属导体被软电介质环绕。金属导体可以包括多个弯曲部分。当设备在零度至摄氏度摄氏八十度的范围内温度循环时，金属导体不会断裂。

56. 发明授权

US07362121B1 Self-heating mechanism for duplicating microbump failure conditions in FPGAs and for logging failures 有权
标题翻译：用于复制FPGA中的微型计算机故障条件和记录故障的自加热机制
公开(公告)号：US07362121B1
公开(公告)日：2008-04-22
申请号：US10860237
申请日：2004-06-02
申请人： Robert O. Conn , Steven J. Carey , Siuki Chan , William H. Pabst
发明人： Robert O. Conn , Steven J. Carey , Siuki Chan , William H. Pabst
IPC分类号： G01R31/02
CPC分类号： G01R31/2875 , G01R31/287 , G01R31/31905
摘要： A system replicates the rapid temperature increases that are believed to cause microbump failures in certain applications of programmable logic devices (PLDs). The system configures a PLD under test with a circuit that switches a large amount of current and generates a large amount of heat when the circuit is clocked. The system monitors the temperature of the PLD and controls the switching of the circuit to achieve a predetermined temperature within a predetermined time period. The PLD is cooled, and the thermal cycling is repeated. The system detects microbump failures and communicates failure data to a computer for logging and analysis.
摘要翻译：系统复制了在可编程逻辑器件（PLD）的某些应用中被认为导致微型块故障的快速升温。该系统通过切换大量电流的电路来配置待测的PLD，并在电路被计时时产生大量的热量。系统监视PLD的温度并控制电路的切换以在预定时间段内达到预定温度。 PLD被冷却，重复热循环。系统检测微型计算机故障，并将故障数据传送到计算机进行记录和分析。

57. 发明授权

US07084487B1 Shielded platform for die-bonding an analog die to an FPGA 有权
标题翻译：用于将模拟芯片与FPGA结合的屏蔽平台
公开(公告)号：US07084487B1
公开(公告)日：2006-08-01
申请号：US10732494
申请日：2003-12-09
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/552
CPC分类号： H01L24/73 , H01L23/34 , H01L23/552 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/82 , H01L24/91 , H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/24145 , H01L2224/24226 , H01L2224/24998 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48235 , H01L2224/49175 , H01L2224/73227 , H01L2224/73265 , H01L2224/73267 , H01L2224/82007 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01013 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit die contains digital circuitry that emits noise (for example, in the audio frequency range) in the form of electromagnetic radiation. The integrated circuit die is provided with a shielded platform above the digital circuitry. The shielded platform has one metal plate that is coupled to an analog supply voltage source and another metal plate that is coupled to an analog ground terminal. The digital circuitry is coupled to a digital supply voltage source. A second die with noise-sensitive analog circuitry is stacked on the shielded platform and is shielded by the shielded platform from the noise. The analog circuitry is powered by the analog supply voltage source. Conductive vias in a predetermined pattern protrude through the shielded platform and provide a standardized way of connecting any one of numerous noise-sensitive second dice to the relatively noisy digital circuitry of the underlying die.
摘要翻译：集成电路管芯包含以电磁辐射的形式发出噪声（例如在音频范围内）的数字电路。集成电路管芯在数字电路之上设置有屏蔽平台。屏蔽平台具有耦合到模拟电源电压源的一个金属板和耦合到模拟接地端子的另一金属板。数字电路耦合到数字电源电压源。具有噪声敏感的模拟电路的第二个芯片堆叠在屏蔽平台上，并被屏蔽平台屏蔽，免受噪音干扰。模拟电路由模拟电源电压供电。具有预定图案的导电孔通过屏蔽平台突出，并提供将多个噪声敏感的第二骰子中的任何一个连接到下面的芯片的相对嘈杂的数字电路的标准化方式。

58. 发明授权

US07064391B1 Bond and back side etchback transistor fabrication process 失效
标题翻译：键合和背面回蚀晶体管制造工艺
公开(公告)号：US07064391B1
公开(公告)日：2006-06-20
申请号：US10824675
申请日：2004-04-14
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L21/8234 , H01L21/30
CPC分类号： H01L27/1203 , H01L21/76256 , H01L21/84 , Y10S438/928
摘要： A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the substrate material of the device wafer. The source and drain regions of the transistor extend into the well region. After attachment of the supporting structure, the device wafer is thinned from the back side until the bottom of the well region is reached. To reduce source and drain junction capacitances, etching can continue until the source and drain regions are reached. In one embodiment, all of the well-to-substrate junction is removed in a subsequent etching step, thereby reducing or eliminating the well-to-substrate junction capacitance of the resulting transistor. Resistance between the well electrode and the transistor channel is reduced because the well contact is disposed on the back side of the device wafer directly under the transistor gate.
摘要翻译：将支撑结构晶片结合到部分或完全处理的器件晶片的上表面侧。器件晶片包括具有延伸到器件晶片的衬底材料中的阱区的晶体管。晶体管的源区和漏极区延伸到阱区。在安装支撑结构之后，装置晶片从后侧变薄直到达到井区的底部。为了减少源极和漏极结电容，可以继续蚀刻直到达到源极和漏极区域。在一个实施例中，在随后的蚀刻步骤中除去所有的阱到衬底结，从而减少或消除所得晶体管的阱到衬底结电容。阱电极和晶体管沟道之间的电阻降低，因为阱触点设置在晶体管栅极正下方的器件晶片的背面。

59. 发明授权

US06961231B1 Interposer providing low-inductance decoupling capacitance for a packaged integrated circuit 有权
公开(公告)号：US06961231B1
公开(公告)日：2005-11-01
申请号：US11074967
申请日：2005-03-08
申请人： Mark A. Alexander , Robert O. Conn , Steven J. Carey
发明人： Mark A. Alexander , Robert O. Conn , Steven J. Carey
IPC分类号： H01G4/232 , H01G4/35 , H01L23/498 , H05K1/02 , H05K1/14 , H05K1/16 , H01G4/06
CPC分类号： H01G4/232 , H01G4/35 , H01L23/49822 , H01L23/49827 , H01L2224/16 , H01L2924/01078 , H01L2924/15311 , H01L2924/19103 , H05K1/0231 , H05K1/141 , H05K1/162 , H05K2201/09309 , H05K2201/10378 , H05K2201/10515 , H05K2201/10734
摘要： Structures that provide decoupling capacitance to packaged IC devices with reduced capacitor and via parasitic inductance. A capacitive interposer structure is physically interposed between the packaged IC and the PCB, thus eliminating the leads and vias that traverse the PCB in known structures. A capacitive interposer is mounted to a PCB and the packaged IC is mounted on the interposer. The interposer has an array of lands on an upper surface, to which the packaged IC is coupled, and an array of terminals on a lower surface, which are coupled to the PCB. Electrically conductive vias interconnect each land with an associated terminal on the opposite surface of the interposer. Within the interposer, layers of a conductive material alternate with layers of a dielectric material, thus forming parallel plate capacitors between adjacent dielectric layers. Each conductive layer is either electrically coupled to, or is electrically isolated from, each via.

60. 发明授权

US06356514B1 Built-in self test method for measuring clock to out delays 有权
标题翻译：内置自检方法，用于测量时钟延迟
公开(公告)号：US06356514B1
公开(公告)日：2002-03-12
申请号：US09816712
申请日：2001-03-23
申请人： Robert W. Wells , Robert D. Patrie , Robert O. Conn
发明人： Robert W. Wells , Robert D. Patrie , Robert O. Conn
IPC分类号： G04F800
CPC分类号： G01R31/3016 , G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/31725 , G01R31/318516 , G01R31/31937
摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the period of the oscillator. The period of the oscillator is then related to the average signal propagation delay through the test circuit. The invention can be applied to synchronous components that might fail to oscillate by connecting the asynchronous set or clear terminal to the output terminal so that the oscillator oscillates at a frequency determined by the clock-to-out delay of those components. The configuration can thus be used to characterize synchronous and asynchronous components to provide data for predicting the timing behavior of circuits that include those or similar components.
摘要翻译：电路通过选定的测试电路测量信号传播延迟。测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。这些信号转换在预定的时间周期内进行计数，以建立振荡器的周期。然后振荡器的周期与通过测试电路的平均信号传播延迟相关。本发明可以应用于通过将异步设置或清除端子连接到输出端子而可能无法振荡的同步部件，使得振荡器以由那些部件的时钟到输出延迟确定的频率振荡。因此，该配置可以用于表征同步和异步组件，以提供用于预测包括那些或类似组件的电路的定时行为的数据。

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