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51. 发明申请

US20100039861A1 NONVOLATILE MEMORY DEVICE AND READ METHOD 有权
标题翻译：非易失性存储器件和读取方法
公开(公告)号：US20100039861A1
公开(公告)日：2010-02-18
申请号：US12506345
申请日：2009-07-21
申请人： Kitae Park , Myoung Gon Kang
发明人： Kitae Park , Myoung Gon Kang
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： Disclosed is a nonvolatile memory including a memory cell array including a first cell string connected between a first bit line and a first common source line, and a second cell string a second common source line and a second bit line adjacent to the first bit line. The nonvolatile memory also includes a control logic circuit configured to independently control the first and second common source lines.
摘要翻译：公开了一种非易失性存储器，包括存储单元阵列，其包括连接在第一位线和第一公共源极线之间的第一单元串，以及第二单元串，与第一位线相邻的第二公共源极线和第二位线。非易失性存储器还包括被配置为独立地控制第一和第二公共源极线的控制逻辑电路。

52. 发明申请

US20100020611A1 FLASH MEMORY SYSTEMS AND OPERATING METHODS USING ADAPTIVE READ VOLTAGE LEVELS 有权
标题翻译：使用自适应读取电压水平的闪存存储器系统和操作方法
公开(公告)号：US20100020611A1
公开(公告)日：2010-01-28
申请号：US12490896
申请日：2009-06-24
申请人： Kitae Park
发明人： Kitae Park
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C11/5642 , G06F11/1068 , G11C16/28 , G11C16/3418 , G11C16/3431 , G11C29/00 , G11C2211/5634
摘要： Some embodiments of the present invention provide methods of operating nonvolatile memory devices. Reference data is stored in a plurality of memory cells. The reference data is read, and a threshold voltage distribution of the plurality of memory cells is determined responsive to reading the reference data. A read voltage of the nonvolatile memory device is modified based on the determined threshold voltage distribution. The nonvolatile memory device may include a main region configured to stored data and a dummy region configured to store the reference data, and the methods may further include reading data from the main region using the modified read voltage.
摘要翻译：本发明的一些实施例提供了操作非易失性存储器件的方法。参考数据存储在多个存储单元中。读取参考数据，并且响应于读取参考数据确定多个存储器单元的阈值电压分布。基于确定的阈值电压分布来修改非易失性存储器件的读取电压。非易失性存储器件可以包括被配置为存储数据的主区域和被配置为存储参考数据的虚拟区域，并且所述方法还可以包括使用修改的读取电压从主区域读取数据。

53. 发明授权

US09864682B2 Nonvolatile memory device and storage device having the same and operation method thereof 有权
公开(公告)号：US09864682B2
公开(公告)日：2018-01-09
申请号：US14664125
申请日：2015-03-20
申请人： Doohyun Kim , BoGeun Kim , Kitae Park , Jinman Han
发明人： Doohyun Kim , BoGeun Kim , Kitae Park , Jinman Han
IPC分类号： G06F12/02 , G11C11/56 , G11C16/04
CPC分类号： G06F12/0246 , G06F2212/7201 , G11C11/5621 , G11C16/0483
摘要： According to example embodiments, a method of operating a storage device includes reading a process capability index using a memory controller, adjusting at least one operation condition based on the process capability index, and operating one of at least one nonvolatile memory device according to the at least one operation condition adjusted. The process capability index indicates how a structure associated with a memory cell to be operated deviates from a target shape.

54. 发明授权

US09424947B2 Nonvolatile memory device and method of program verifying the same 有权
标题翻译：非易失性存储器件和程序验证方法
公开(公告)号：US09424947B2
公开(公告)日：2016-08-23
申请号：US14284031
申请日：2014-05-21
申请人： Donghun Kwak , Hyun-Wook Park , Kitae Park
发明人： Donghun Kwak , Hyun-Wook Park , Kitae Park
IPC分类号： G11C16/34 , G11C16/10 , G11C16/26 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/26
摘要： A program method of a three-dimensional nonvolatile memory device is provided which includes executing at least one program loop including an operation of programming selected memory cells of a selected string turned on by a selected string selection transistor and an operation of verifying whether programming of the memory cells is passed; and applying a negative counter voltage to a selected word line connected to the selected memory cells of the selected string at least once during an interval of the verify operation where there are turned on string selection transistors of unselected strings connected through the same bit line as that of the selected string.
摘要翻译：提供了一种三维非易失性存储器件的编程方法，包括执行至少一个程序循环，该程序循环包括对由所选择的字符串选择晶体管导通的所选字符串的选定存储单元进行编程的操作，以及验证是否记忆细胞通过; 以及在验证操作的间隔期间至少一次将连接到所选字符串的所选择的存储单元的选定字线施加负的反电压，其中通过与该相同的位线连接的未选择的串连接的串选择晶体管，的所选字符串。

55. 发明授权

US09026749B2 Data storage system having multi-bit memory device and on-chip buffer program method thereof 有权
标题翻译：具有多位存储器件的数据存储系统及其片上缓冲器程序方法
公开(公告)号：US09026749B2
公开(公告)日：2015-05-05
申请号：US13484712
申请日：2012-05-31
申请人： Sangyong Yoon , Kitae Park
发明人： Sangyong Yoon , Kitae Park
IPC分类号： G06F12/00 , G11C11/56 , G06F12/02 , G11C16/34
CPC分类号： G11C11/5628 , G06F12/0246 , G06F2212/7203 , G11C16/3418 , G11C16/3454 , G11C2211/5641
摘要： Disclosed is an on-chip buffer program method for a data storage device which comprises a multi-bit memory device and a memory controller. The on-chip buffer program method includes measuring a performance of the data storage device, judging whether the measured performance satisfies a target performance of the data storage device, and selecting one of a plurality of scheduling manners as an on-chip buffer program scheduling manner of the data storage device according to the judgment result.
摘要翻译：公开了一种用于数据存储设备的片上缓冲器程序方法，其包括多位存储器件和存储器控制器。片上缓冲程序方法包括测量数据存储装置的性能，判断测量性能是否满足数据存储装置的目标性能，并选择多种调度方式之一作为片上缓冲程序调度方式的数据存储装置。

56. 发明授权

US09021338B2 Memory system and data storage method 有权
标题翻译：内存系统和数据存储方式
公开(公告)号：US09021338B2
公开(公告)日：2015-04-28
申请号：US13604772
申请日：2012-09-06
申请人： Sang-Hyun Joo , Kitae Park , Sangyong Yoon , Jaeyong Jeong
发明人： Sang-Hyun Joo , Kitae Park , Sangyong Yoon , Jaeyong Jeong
IPC分类号： G06F11/10 , G11C29/42 , G06F3/06 , H03M13/05 , H03M13/37 , G06F12/02 , G06F11/14
CPC分类号： G06F11/1048 , G06F3/0649 , G06F11/1068 , G06F11/14 , G06F11/1402 , G06F12/0246 , G06F2212/72 , G06F2212/7205 , G11C29/42 , G11C2211/5641 , H03M13/05 , H03M13/3715
摘要： A memory system comprises a nonvolatile memory device comprising a memory cell array comprising first and second memory blocks, and a memory controller configured to control the nonvolatile memory device to read data from the first memory block, selectively determine an error correction operation to be performed on the data after it is read from the first memory block based on a state of at least one of the first and second memory blocks, and then store the data in the second memory block.
摘要翻译：存储器系统包括非易失性存储器件，其包括包括第一和第二存储器块的存储器单元阵列，以及存储器控制器，其被配置为控制非易失性存储器件从第一存储器块读取数据，选择性地确定要执行的纠错操作基于第一和第二存储器块中的至少一个的状态从第一存储器块读取之后的数据，然后将数据存储在第二存储器块中。

57. 发明授权

US08902666B2 Programming method for nonvolatile memory device 有权
标题翻译：非易失性存储器件的编程方法
公开(公告)号：US08902666B2
公开(公告)日：2014-12-02
申请号：US13443053
申请日：2012-04-10
申请人： Sangyong Yoon , Kitae Park
发明人： Sangyong Yoon , Kitae Park
IPC分类号： G11C11/34 , G11C16/06 , G11C16/34 , G11C16/10 , G11C11/56
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A method of programming memory cells (transistors) of a nonvolatile memory device from a first set of (previous) logic states to a second set of (final) logic states. The method includes applying program voltages to selected memory transistors; and applying a pre-verification voltage and a target verification voltage for verifying the current logic state of the selected memory transistors. The voltage interval between logic states of the second set of logic states is less than the voltage interval between logic states of the first set of logic states. A target verification voltage for verifying a first memory transistor is at one logic state of the second set is used as a pre-verification voltage for verifying that a second memory transistor to be programmed to higher logic state of the second set.
摘要翻译：一种将非易失性存储器件的存储单元（晶体管）从第一组（先前）逻辑状态编程到第二组（最终）逻辑状态的方法。该方法包括将程序电压施加到选定的存储晶体管; 以及施加预验证电压和目标验证电压以验证所选存储晶体管的当前逻辑状态。第二组逻辑状态的逻辑状态之间的电压间隔小于第一组逻辑状态的逻辑状态之间的电压间隔。用于验证第一存储晶体管的目标验证电压处于第二组的一个逻辑状态，用作预验证电压，用于验证将第二存储晶体管编程为第二组的较高逻辑状态。

58. 发明授权

US08861276B2 Nonvolatile memory device, memory system comprising same, and method of operating same 有权
标题翻译：非易失性存储器件，包括其的存储器系统及其操作方法
公开(公告)号：US08861276B2
公开(公告)日：2014-10-14
申请号：US13527641
申请日：2012-06-20
申请人： Dongkyo Shim , Jaeyong Jeong , Ju Seok Lee , Ohsuk Kwon , Kitae Park , Hyunjun Yoon
发明人： Dongkyo Shim , Jaeyong Jeong , Ju Seok Lee , Ohsuk Kwon , Kitae Park , Hyunjun Yoon
IPC分类号： G11C16/26 , G11C16/04 , G11C11/56
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483
摘要： A method of operating a nonvolatile memory device comprises receiving a read command from a memory controller, determining a read mode of the nonvolatile memory device, selecting a read voltage based on the read mode, and performing a read operation on memory cells of a selected page of the nonvolatile memory device using the selected read voltage.
摘要翻译：一种操作非易失性存储器件的方法包括从存储器控制器接收读取命令，确定非易失性存储器件的读取模式，基于读取模式选择读取电压，以及对所选择的页面的存储器单元执行读取操作使用所选择的读取电压的非易失性存储器件。

59. 发明授权

US08788908B2 Data storage system having multi-bit memory device and on-chip buffer program method thereof 有权
标题翻译：具有多位存储器件的数据存储系统及其片上缓冲器程序方法
公开(公告)号：US08788908B2
公开(公告)日：2014-07-22
申请号：US13225676
申请日：2011-09-06
申请人： Sangyong Yoon , Kitae Park
发明人： Sangyong Yoon , Kitae Park
IPC分类号： G11C29/00
CPC分类号： G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C2029/0411 , G11C2211/5641
摘要： A data storage device includes a multi-bit memory device including a memory cell array, the memory cell array including a first memory region and a second memory region, and a memory controller including a buffer memory and configured to control the multi-bit memory device. The memory controller is configured to control the multi-bit memory device to execute a buffer program operation in which data stored in the buffer memory is stored in the first memory region, and to control the multi-bit memory device to execute a main program operation in which the data stored in the first memory region is stored in the second memory region. The memory controller is further configured to generate parity data based upon the data stored to the first region, the parity data being copied from the first memory region to the second memory region via the main program operation.
摘要翻译：数据存储装置包括包括存储单元阵列的多位存储器件，所述存储单元阵列包括第一存储器区域和第二存储器区域，以及包括缓冲存储器并被配置为控制所述多位存储器件的存储器控制器。存储器控制器被配置为控制多位存储器件执行缓冲器程序操作，其中存储在缓冲存储器中的数据存储在第一存储器区域中，并且控制多位存储器件执行主程序操作其中存储在第一存储器区域中的数据被存储在第二存储器区域中。存储器控制器还被配置为基于存储到第一区域的数据，经由主程序操作将奇偶校验数据从第一存储器区域复制到第二存储器区域来生成奇偶校验数据。

60. 发明授权

US08665643B2 Non-volatile memory device and read method thereof 有权
标题翻译：非易失性存储器件及其读取方法
公开(公告)号：US08665643B2
公开(公告)日：2014-03-04
申请号：US13416038
申请日：2012-03-09
申请人： Tae-Young Kim , Jongsun Sel , Kitae Park
发明人： Tae-Young Kim , Jongsun Sel , Kitae Park
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G06F11/073 , G06F11/076 , G11C11/5642 , G11C16/26 , G11C2211/5642
摘要： Disclosed is a non-volatile memory device which includes a memory cell array having memory cells arranged in rows and columns, a page buffer circuit configured to read data from the memory cell array, and a control logic and input/output interface block including a normal read scheduler controlling a normal read operation and a data recover read scheduler controlling a data recover read operation and configured to control the page buffer circuit at a read request. One of the normal read scheduler and the data recover read scheduler is selected according to selection information provided from an external device.
摘要翻译：公开了一种非易失性存储器件，其包括具有以行和列排列的存储单元的存储单元阵列，被配置为从存储单元阵列读取数据的页缓冲器电路以及包括正常的控制逻辑和输入/输出接口块控制正常读取操作的读取调度器和控制数据恢复读取操作的数据恢复读取调度器，并且被配置为在读取请求时控制页面缓冲器电路。根据从外部设备提供的选择信息来选择正常读取调度器和数据恢复读取调度器之一。

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