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51. 发明申请

US20060286758A1 Super anneal for process induced strain modulation 有权
公开(公告)号：US20060286758A1
公开(公告)日：2006-12-21
申请号：US11199011
申请日：2005-08-08
申请人： Mong Liang , Chien-Hao Chen , Chun-Feng Nieh , Pang-Yen Tsai , Tze-Liang Lee , Shih-Chang Chen
发明人： Mong Liang , Chien-Hao Chen , Chun-Feng Nieh , Pang-Yen Tsai , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/7624 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so that the stressor layer is super annealed for a substantially short duration. Preferably, the method further includes masking a second device region on the substrate while the first device region is super annealed. Alternatively, after the stressor layer in the first region is annealed, the stressor layer in the second device region is super annealed. A semiconductor structure formed using the method has different strains in the first and second device regions.

52. 发明申请

US20060244074A1 Hybrid-strained sidewall spacer for CMOS process 审中-公开
标题翻译：用于CMOS工艺的混合应变侧壁间隔件
公开(公告)号：US20060244074A1
公开(公告)日：2006-11-02
申请号：US11119272
申请日：2005-04-29
申请人： Chien-Hao Chen , Kai-Ting Tseng , Tze-Liang Lee
发明人： Chien-Hao Chen , Kai-Ting Tseng , Tze-Liang Lee
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/4966 , H01L29/7843
摘要： Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their gate electrode sidewall spacers are fabricated such that the orientation of the intrinsic stress in the sidewall spacers is opposite to the stress created in the channel. An embodiment includes selectively patterning a compressive stress layer to form NMOS electrode sidewall spacers, wherein the compressive NMOS electrode sidewall spacers create a tensile stress in a NMOS channel. Another embodiment comprises selectively patterning a tensile stress layer to form tensile PMOS electrode sidewall spacers, wherein the PMOS electrode sidewall spacers create a compressive stress in a PMOS channel. Still other embodiments of the invention provide a semiconductor device having strained sidewall spacers. In one embodiment, a spacer having an intrinsic stress comprising one of tensile and compressive corresponds to a channel stress that is the other of tensile and compressive.
摘要翻译：本发明的实施例提供一种半导体器件和制造方法。 MOS器件及其栅电极侧壁间隔件被制造成使得侧壁间隔物中的本征应力的取向与在通道中产生的应力相反。一个实施例包括选择性地图案化压应力层以形成NMOS电极侧壁间隔物，其中压电NMOS电极侧壁间隔件在NMOS沟道中产生拉伸应力。另一个实施例包括选择性地图案化拉伸应力层以形成拉伸PMOS电极侧壁间隔物，其中PMOS电极侧壁间隔件在PMOS沟道中产生压缩应力。本发明的其它实施例提供了具有应变侧壁间隔物的半导体器件。在一个实施例中，具有包括拉伸和压缩中的一个的本征应力的间隔物对应于作为拉伸和压缩的另一个的通道应力。

53. 发明申请

US20060186470A1 Strained transistor with hybrid-strain inducing layer 有权
标题翻译：具有杂化应变诱导层的应变晶体管
公开(公告)号：US20060186470A1
公开(公告)日：2006-08-24
申请号：US11062723
申请日：2005-02-22
申请人： Chien-Hao Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Tze-Liang Lee
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/4983 , H01L29/66628 , H01L29/66636 , H01L29/7843
摘要： A semiconductor device having a hybrid-strained layer and a method of forming the same are discussed. The semiconductor device comprises: a gate dielectric over a substrate; a gate electrode over the gate dielectric; an optional pair of spacers along the sidewalls of the gate dielectric and the gate electrode; a source/drain region substantially aligned with an edge of the gate electrode; and a strained layer over the source/drain region, gate electrode, and spacers wherein the strained layer has a first portion and a second portion. The first portion of the strained layer is substantially over the source/drain region and has a first inherent strain. The second portion of the strained layer has at least a portion substantially over the gate electrode and the spacers and has a second inherent strain of the opposite type of the first strain.
摘要翻译：讨论了具有混合应变层的半导体器件及其形成方法。半导体器件包括：衬底上的栅极电介质; 位于栅极电介质上的栅电极; 沿着栅极电介质和栅电极的侧壁的可选的一对间隔物; 源极/漏极区域，其基本上与栅电极的边缘对齐; 以及源极/漏极区域上的应变层，栅电极和间隔物，其中应变层具有第一部分和第二部分。应变层的第一部分基本上在源极/漏极区域之上并且具有第一固有应变。应变层的第二部分具有基本上在栅电极和间隔物上的至少一部分，并且具有相反类型的第一应变的第二固有应变。

54. 发明申请

US20060125028A1 MOSFET device with localized stressor 有权
标题翻译：具有局部应力源的MOSFET器件
公开(公告)号：US20060125028A1
公开(公告)日：2006-06-15
申请号：US11012413
申请日：2004-12-15
申请人： Chien-Hao Chen , Donald Chao , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Donald Chao , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L29/7833 , H01L29/6659 , H01L29/7843
摘要： A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress film for use with p-channel devices. A method of fabricating a MOSFET with localized stressors over the source/drain regions comprises forming a transistor having a gate electrode and source/drain regions, forming a high-stress film over the gate electrode and the source/drain regions, and thereafter removing the high-stress film located over the gate electrode, thereby leaving the high-stress film located over the source/drain regions. A contact-etch stop layer may be formed over the transistor.
摘要翻译：提供了具有局部应力源的金属氧化物半导体场效应晶体管（MOSFET）。根据本发明的实施例，晶体管包括源/漏区上的高应力膜，但不在栅电极上。高应力膜可以是用于n沟道器件的拉伸应力膜或用于p沟道器件的压应力膜。在源极/漏极区域上制造具有局部应力源的MOSFET的方法包括形成具有栅电极和源/漏区的晶体管，在栅电极和源/漏区上形成高应力膜，然后除去高应力膜位于栅电极之上，从而使高应力膜位于源极/漏极区之上。接触蚀刻停止层可以形成在晶体管上。

55. 发明申请

US20050253194A1 SOI-like structure in a bulk semiconductor substrate and method of forming same 有权
标题翻译：体半导体衬底中的SOI类结构及其形成方法
公开(公告)号：US20050253194A1
公开(公告)日：2005-11-17
申请号：US10847607
申请日：2004-05-17
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/324 , H01L21/762 , H01L27/01 , H01L27/12
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.
摘要翻译：通过退火将体硅转变成SOI样结构。沟槽形成在大量衬底中以限定器件位置。沟槽的下部在氢气气氛中在低压下退火。这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。相邻的空洞每个居住在中间位置的一半左右。消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

56. 发明申请

US20050218476A1 Integrated process for fuse opening and passivation process for Cu/Low-K IMD 审中-公开
标题翻译： Cu / Low-K IMD的保险丝开路和钝化工艺的综合工艺
公开(公告)号：US20050218476A1
公开(公告)日：2005-10-06
申请号：US11132086
申请日：2005-05-18
申请人： Tze-Liang Lee , Chao-Chen Chen
发明人： Tze-Liang Lee , Chao-Chen Chen
IPC分类号： H01L21/44 , H01L23/48 , H01L23/525
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A new process flow is provided for the creation of a fuse contact and a bond pad. The invention starts with a semiconductor substrate over the surface of which is provided top level metal and fuse metal in the surface of a layer of insulation deposited over the surface of the substrate. A first etch stop layer is deposited over the surface of the layer of insulation over which a first passivation layer is deposited, an opening is created through these layers exposing the top level metal. A metal plug is created overlying the exposed surface of the top level metal. A stack of a patterned and etched hard mask layers, having been deposited at part of the creation of the metal plug and overlying a layer of metal plug material, remains in place over the surface of the created metal plug. A second layer of passivation material is deposited, the second layer of passivation is patterned and etched exposing the surface of the first layer of passivation overlying the fuse metal and exposing the surface of the stack of hard mask layers overlying the created metal plug. The stack of hard mask layers is then removed from the surface of the metal plug, exposing the surface of the metal plug to serve as a contact pad and further reducing the thickness of the first layer of passivation over the surface of the fuse metal, making the fuse more accessible for fuse blowing.
摘要翻译：提供了一种新的工艺流程来创建保险丝触点和接合垫。本发明从其表面上提供顶层金属和熔丝金属的半导体衬底开始沉积在衬底表面上的绝缘层表面。第一蚀刻停止层沉积在绝缘层的表面上，在绝缘层的表面上沉积第一钝化层，通过暴露顶层金属的这些层产生开口。在顶层金属的暴露表面上形成一个金属塞。已经沉积在金属插塞的一部分并且覆盖一层金属插塞材料的图案和蚀刻的硬掩模层的堆叠保持在所产生的金属插塞的表面上的适当位置。沉积第二层钝化材料，第二层钝化被图案化和蚀刻，暴露第一层钝化层的表面，覆盖熔丝金属并暴露覆盖所产生的金属插塞的硬掩模层堆叠的表面。然后从金属塞的表面去除堆叠的硬掩模层，暴露金属塞的表面以用作接触焊盘，并进一步减小熔丝金属表面上的第一钝化层的厚度，使得保险丝更容易熔断。

57. 发明申请

US20050159008A1 High temperature hydrogen annealing of a gate insulator layer to increase etching selectivity between conductive gate structure and gate insulator layer 有权
标题翻译：栅极绝缘体层的高温氢退火以增加导电栅极结构和栅极绝缘体层之间的蚀刻选择性
公开(公告)号：US20050159008A1
公开(公告)日：2005-07-21
申请号：US10758317
申请日：2004-01-15
申请人： Vincent Chang , Chia-Lin Chen , Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen , Chien-Hao Chen
发明人： Vincent Chang , Chia-Lin Chen , Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen , Chien-Hao Chen
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/311 , H01L21/314 , H01L21/3213 , H01L21/336 , H01L21/477 , H01L29/51
CPC分类号： H01L29/518 , H01L21/28123 , H01L21/28185 , H01L21/28202 , H01L21/3105 , H01L21/3144 , H01L21/32137 , H01L29/6659
摘要： A method of defining a conductive gate structure for a MOSFET device wherein the etch rate selectivity of the conductive gate material to an underlying insulator layer is optimized, has been developed. After formation of a nitrided silicon dioxide layer, to be used as for the MOSFET gate insulator layer, a high temperature hydrogen anneal procedure is performed. The high temperature anneal procedure replaces nitrogen components in a top portion of the nitrided silicon dioxide gate insulator layer with hydrogen components. The etch rate of the hydrogen annealed layer in specific dry etch ambients is now decreased when compared to the non-hydrogen annealed nitrided silicon dioxide counterpart. Thus the etch rate selectivity of conductive gate material to underlying gate insulator material is increased when employing the slower etching hydrogen annealed nitrided silicon dioxide layer.
摘要翻译：已经开发了限定用于MOSFET器件的导电栅极结构的方法，其中导电栅极材料对下面的绝缘体层的蚀刻速率选择性被优化。在形成用于MOSFET栅极绝缘体层的氮化二氧化硅层之后，进行高温氢退火处理。高温退火程序用氢组分替代氮化二氧化硅栅极绝缘体层的顶部中的氮组分。当与非氢退火氮化二氧化硅对应物相比时，特定干蚀刻环境中的氢退火层的蚀刻速率现在降低。因此，当采用较慢的蚀刻氢退火氮化二氧化硅层时，导电栅极材料对底层栅极绝缘体材料的蚀刻速率选择性增加。

58. 发明授权

US06864109B2 Method and system for determining a component concentration of an integrated circuit feature 失效
标题翻译：用于确定集成电路特征的元件浓度的方法和系统
公开(公告)号：US06864109B2
公开(公告)日：2005-03-08
申请号：US10625410
申请日：2003-07-23
申请人： Vincent S. Chang , Chi-Chun Chen , Chun-Lin Wu , Tze-Liang Lee , Shih-Chang Chen
发明人： Vincent S. Chang , Chi-Chun Chen , Chun-Lin Wu , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： G01N21/71 , H01L21/314 , H01L29/78 , H01L21/26 , H01L21/66
CPC分类号： H01J37/32935 , G01N21/71 , H01L21/28202 , H01L21/3144 , H01L29/7833
摘要： A method of determining a composition of an integrated circuit feature, including collecting intensity data representative of spectral wavelengths of radiant energy generated by a plasma during plasma nitridation of an integrated circuit feature disposed on a substrate, analysing the in intensity data to determine a peak intensity at one of the wavelengths, and determining a component concentration of the feature based on the peak intensity.
摘要翻译：一种确定集成电路特征的组成的方法，包括收集表示在等离子体中等离子体产生的辐射能的光谱波长的强度数据，所述等离子体在等离子体氮化期间设置在基板上的集成电路特征，分析强度数据以确定峰强度在一个波长处，并且基于峰值强度确定特征的分量浓度。

59. 发明申请

US20050019964A1 METHOD AND SYSTEM FOR DETERMINING A COMPONENT CONCENTRATION OF AN INTEGRATED CIRCUIT FEATURE 失效
标题翻译：用于确定集成电路特征的组分浓度的方法和系统
公开(公告)号：US20050019964A1
公开(公告)日：2005-01-27
申请号：US10625410
申请日：2003-07-23
申请人： Vincent Chang , Chi-Chun Chen , Chun-Lin Wu , Tze-Liang Lee , Shih-Chang Chen
发明人： Vincent Chang , Chi-Chun Chen , Chun-Lin Wu , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： G01N21/71 , H01L21/314 , H01L29/78 , H01L21/66
CPC分类号： H01J37/32935 , G01N21/71 , H01L21/28202 , H01L21/3144 , H01L29/7833
摘要： A method of determining a composition of an integrated circuit feature, including collecting intensity data representative of spectral wavelengths of radiant energy generated by a plasma during plasma nitridation of an integrated circuit feature disposed on a substrate, analyzing the intensity data to determine a peak intensity at one of the wavelengths, and determining a component concentration of the feature based on the peak intensity.
摘要翻译：一种确定集成电路特征的组成的方法，包括收集表示在等离子体中等离子体产生的辐射能的光谱波长的强度数据，所述等离子体在等离子体氮化期间设置在衬底上的集成电路特征，分析强度数据以确定峰强度一个波长，并且基于峰值强度确定特征的分量浓度。

60. 发明授权

US06642117B1 Method for forming composite dielectric layer 有权
标题翻译：复合介电层形成方法
公开(公告)号：US06642117B1
公开(公告)日：2003-11-04
申请号：US10213117
申请日：2002-08-05
申请人： Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3144 , H01L21/31662 , H01L29/513 , H01L29/518
摘要： A method for forming a dielectric layer provides that a oxidizable substrate has formed thereupon a thermal oxide layer in turn having formed thereupon a deposited nitride layer. The deposited nitride/thermal oxide stack layer is then sequentially: (1) annealed within a nitriding atmosphere; (2) annealed within an oxidizing atmosphere; and (3) treated with a vaporous hydrofluoric acid atmosphere. The annealed and treated stack layer provides, for example, a gate dielectric layer with diminished thickness and enhanced performance.
摘要翻译：形成电介质层的方法提供了可氧化衬底在其上形成有依次形成沉积氮化物层的热氧化层。沉积的氮化物/热氧化物堆叠层然后依次：（1）在氮化气氛中退火; （2）在氧化气氛中退火; 和（3）用氢氟酸气氛处理。退火和处理的堆叠层提供例如具有减小的厚度和增强的性能的栅极电介质层。

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