专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US06292924B1 Modifying timing graph to avoid given set of paths 失效
标题翻译：修改时序图以避免给定的路径集
公开(公告)号：US06292924B1
公开(公告)日：2001-09-18
申请号：US08964997
申请日：1997-11-05
申请人： Ivan Pavisic , Anatoli A. Bolotov , Alexander E. Andreev , Ranko Scepanovic
发明人： Ivan Pavisic , Anatoli A. Bolotov , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. In order to design circuits to meet a given set of requirements, each signal path of the circuit must be analyzed. Because of the large number of the cells and the complex connections, the number of paths is very large and requires much computing power to analyze. Also, some of the paths are not important for the purposes of the operations of the chip and can be discounted during the analysis process. The present invention discloses a method and apparatus used to avoid analyzing non-important paths, referred to as false paths of a directed timing graph. To avoid the false paths, the timing graph representing the circuit is modified to exclude the false paths before the graph is analyzed. To modify the timing graph, duplicate nodes are constructed, duplicate edges are constructed, and some edges of the original graph are cut and replaced by mixed edges connecting non-duplicate nodes to duplicate nodes. Finally, mixed edges are created to connect duplicate nodes to non-duplicate nodes, integrating the duplicate graph with the original graph.
摘要翻译：集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。 IC的设计需要满足实际的限制，例如最小化电路面积，最小化电路内的电线长度，以及使IC执行其功能所需的时间最小化，称为IC延迟。为了设计电路以满足给定的一组要求，必须分析电路的每个信号路径。由于大量的单元和复杂的连接，路径数量非常多，需要很多计算能力进行分析。此外，一些路径对于芯片的操作的目的不重要，并且可以在分析过程期间被折扣。本发明公开了一种用于避免分析非重要路径的方法和装置，被称为定向定时图的假路径。为了避免错误路径，修改表示电路的时序图，以排除图表分析之前的虚假路径。为了修改时序图，构造了重复的节点，构建了重复的边，原始图的一些边被剪切，并将不重复的节点连接到重复节点的混合边替换。最后，创建混合边以将重复节点连接到非重复节点，将重复图与原始图集成。

IPRDB

热门服务

关于我们

友情链接

联系方式