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51. 发明授权

US5708843A Method and apparatus for handling code segment violations in a computer system 失效
标题翻译：在计算机系统中处理代码段违规的方法和装置
公开(公告)号：US5708843A
公开(公告)日：1998-01-13
申请号：US544558
申请日：1995-10-18
申请人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Rohit Vidwans
发明人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Rohit Vidwans
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3865
摘要： A memory operation is issued in a processor. Upon detecting both that the memory operation produces a code segment violation and that the memory operation is blocked at retirement, a blocking signal is produced to block a bus access responsive to the memory operation. A second signal signifies that the memory operation completed.
摘要翻译：在处理器中发出存储器操作。在检测到存储器操作产生代码段违反并且在退出时存储器操作被阻止的情况下，产生阻塞信号以阻止响应于存储器操作的总线访问。第二个信号表示内存操作完成。

52. 发明授权

US5584001A Branch target buffer for dynamically predicting branch instruction outcomes using a predicted branch history 失效
标题翻译：分支目标缓冲区，用于使用预测的分支历史动态预测分支指令结果
公开(公告)号：US5584001A
公开(公告)日：1996-12-10
申请号：US509331
申请日：1995-07-31
申请人： Bradley D. Hoyt , Glenn J. Hinton , Andrew F. Glew , Subramanian Natarajan
发明人： Bradley D. Hoyt , Glenn J. Hinton , Andrew F. Glew , Subramanian Natarajan
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3806 , G06F9/3844
摘要： A branch prediction mechanism that maintains both speculative history and actual history for each branch instruction in a branch target buffer. The actual branch history contains the branch history for fully resolved occurrences of the branch instruction. The speculative branch history contains the actual history plus the "history" of recent branch predictions for the branch. If the speculative branch history contains any recent predictions, then a speculation bit is set. When the speculation bit is set, this indicates that there is speculative history for a branch. Therefore, when the speculation bit is set the speculative history is used to make branch predictions. If a misprediction is made for the branch, the speculation bit is cleared since the speculative history contains inaccurate branch history.
摘要翻译：分支预测机制，保持分支目标缓冲区中每个分支指令的推测历史和实际历史。实际的分支历史包含分支指令的完全解决事件的分支历史。投机分支历史包含实际历史加上分支机构最近分支预测的“历史”。如果推测分支历史记录包含任何最近的预测，则设置推测位。当猜测位置位时，表示有一个分支的推测历史。因此，当设置推测位时，推测历史用于进行分支预测。如果对分行进行错误预测，则推测位将被清除，因为投机历史记录包含不准确的分支历史记录。

53. 发明授权

US06378062B1 Method and apparatus for performing a store operation 失效
标题翻译：用于执行存储操作的方法和装置
公开(公告)号：US06378062B1
公开(公告)日：2002-04-23
申请号：US08825427
申请日：1997-03-28
申请人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
发明人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
IPC分类号： G06F930
CPC分类号： G06F9/3855 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： The present invention provides for executing store instructions with a processor. The present invention executes each of the store instructions by producing the data that is to be stored and by calculating the destination address to which the data is to be stored. In the present invention, the store instructions are executed to produce the destination address of the store instruction earlier than the prior art.
摘要翻译：本发明提供用处理器执行存储指令。本发明通过产生要存储的数据并通过计算要存储数据的目的地地址来执行每个存储指令。在本发明中，执行存储指令以比现有技术更早地产生存储指令的目的地地址。

54. 发明授权

US5881262A Method and apparatus for blocking execution of and storing load operations during their execution 失效
标题翻译：用于在其执行期间阻止执行和存储加载操作的方法和装置
公开(公告)号：US5881262A
公开(公告)日：1999-03-09
申请号：US928924
申请日：1997-09-12
申请人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
发明人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
IPC分类号： G06F9/312 , G06F9/38 , G06F13/00
CPC分类号： G06F9/3017 , G06F9/30043 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3842
摘要： A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present invention halts the execution of the load operation when a dependency exists between the load operation and another memory operation currently pending in the system. When the dependency no longer exists, the present invention redispatches the load operation so that it completes.
摘要翻译：一种用于在计算机系统中执行加载操作的方法和装置。本发明包括一种用于调度要执行的加载操作的方法和装置。本发明在加载操作和系统中当前待处理的另一个存储器操作之间存在依赖关系时，停止加载操作的执行。当依赖关系不再存在时，本发明重新分派加载操作使其完成。

55. 发明授权

US5751996A Method and apparatus for processing memory-type information within a microprocessor 失效
标题翻译：用于处理微处理器内的存储器类型信息的方法和装置
公开(公告)号：US5751996A
公开(公告)日：1998-05-12
申请号：US767799
申请日：1996-12-17
申请人： Andrew F. Glew , Glenn J. Hinton
发明人： Andrew F. Glew , Glenn J. Hinton
IPC分类号： G06F9/312 , G06F9/38 , G06F12/08
CPC分类号： G06F9/30043 , G06F12/0804 , G06F12/0888 , G06F9/3824 , G06F9/3842 , G06F9/3857
摘要： A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor. Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined for the memory location identified by the memory micro-instruction. Once the memory-type is known the memory micro-instruction is processed in accordance with any one of a number of processing protocols including write-through processing, write-back processing, write-protect processing, restricted-cacheability processing, uncacheable speculatable write-combining processing, or uncacheable processing. By providing memory-type information explicitly within the microprocessor, the type of memory identified by a micro-instruction is known before the micro-instruction is processed. Accordingly, the protocol by which the micro-instruction is processed may be efficiently tailored to the memory-type. For example, if the memory location identified by the micro-instruction is known to be uncacheable, a data cache unit is bypassed and external memory is accessed directly. In an exemplary embodiment, the microprocessor is an out-of-order microprocessor capable of generating speculative memory micro-instruction. Also, the microprocessor may be only one of a number of microprocessors within a multiprocessor system.
摘要翻译：识别包含有存储器位置范围的存储器类型的存储器类型值被明确地存储在微处理器内。在处理诸如加载或存储之类的存储器微指令之前，为由存储器微指令识别的存储器位置确定存储器类型。一旦已知存储器类型，存储器微指令根据多种处理协议中的任何一种被处理，包括直写处理，回写处理，写保护处理，限制高速缓存处理，不可缓存的可写入写入 - 组合处理或不可缓解的处理。通过在微处理器内显式提供存储器类型信息，在微指令被处理之前，已经知道由微指令识别的存储器类型。因此，处理微指令的协议可以有效地针对存储器类型进行定制。例如，如果由微指令识别的存储器位置已知是不可缓存的，则旁路数据高速缓存单元，并直接访问外部存储器。在示例性实施例中，微处理器是能够产生推测存储器微指令的无序微处理器。此外，微处理器可能只是多处理器系统内的多个微处理器之一。

56. 发明授权

US5671444A Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers 失效
标题翻译：使用多个填充缓冲器以非阻塞方式高速缓存数据的方法和装置
公开(公告)号：US5671444A
公开(公告)日：1997-09-23
申请号：US731545
申请日：1996-10-15
申请人： Haitham Akkary , Jeffrey M. Abramson , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , Mandar S. Joshi , Brent E. Lince
发明人： Haitham Akkary , Jeffrey M. Abramson , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , Mandar S. Joshi , Brent E. Lince
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0859 , G06F12/0831
摘要： A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.
摘要翻译：具有对应的标签匹配电路的数据高速缓存和多个伴随填充缓冲器被提供给计算机系统。每个填充缓冲器独立地存储和跟踪填充有响应于高速缓存未命中从主存储器返回的数据的替换高速缓存行。当缓存填充完成时，如果内存位置是可高速缓存的，并且缓存填充正在进行时，缓存线尚未被窥探，则会为高速缓存标签和数据高速缓存的数据阵列输出替换高速缓存行。此外，填充缓冲区被组织并提供有足够的地址和数据端口以及选择器，以允许填充缓冲区响应后续处理器负载和存储，以及在高速缓存填充正在进行时触发其缓存行的外部监听。因此，数据高速缓存的高速缓存标签和数据阵列可以在一个或多个缓存填充正在进行的同时继续提供后续的处理器加载和存储以及外部监听，而无需停止处理器。

57. 发明授权

US5903751A Method and apparatus for implementing a branch target buffer in CISC processor 失效
标题翻译：在CISC处理器中实现分支目标缓冲器的方法和装置
公开(公告)号：US5903751A
公开(公告)日：1999-05-11
申请号：US931807
申请日：1997-09-16
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054
摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.
摘要翻译：公开了一种使用计算机指令流预测分支指令的计算机处理器中的分支目标缓冲器电路。分支目标缓冲器电路使用分支目标缓冲器高速缓存，其存储关于先前执行的分支指令的分支信息。存储在分支目标缓冲区高速缓存中的分支信息由每个分支指令的最后一个字节寻址。当计算机处理器中的指令获取单元获取指令块时，它向分支目标缓冲器电路发送指令指针。基于指令指针，分支目标缓冲器电路查找分支目标缓冲区高速缓存以查看正在获取的块中的任何指令是否是分支指令。当分支目标缓冲器电路在分支目标缓冲器高速缓存中找到即将到来的分支指令时，分支目标缓冲器电路通知指令获取单元关于即将到来的分支指令。

58. 发明授权

US5586278A Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor 失效
标题翻译：在无序微处理器中的分支错误预测之后状态恢复的方法和装置
公开(公告)号：US5586278A
公开(公告)日：1996-12-17
申请号：US639244
申请日：1996-04-22
申请人： David B. Papworth , Glenn J. Hinton
发明人： David B. Papworth , Glenn J. Hinton
IPC分类号： G06F9/38
CPC分类号： G06F9/3863
摘要： A method of state recovery following a branch misprediction or an undetected branch instruction. If, during execution of a branch instruction in an out-of-order unit, it is determined that the branch has been mispredicted, or if a taken branch has not been detected, then a JEClear signal is asserted to flush the instruction fetch unit and decoder section, and to change the instruction pointer to the actual target address. Within the out-of-order section, the instructions preceding the branch instruction are allowed to continue execution and proceed to in-order retirement. Simultaneously, instructions fetched at the actual target address are decoded, but not allowed to issue therefrom until the branch instruction has been retired from the out-of-order section, after which all instructions within the out-of-order section are flushed, and then decoded instructions are allowed to issue from the decoder. The state recovery method advantageously provides efficient utilization of processor time.
摘要翻译：分支错误预测或未检测到的分支指令之后的状态恢复方法。如果在执行无序单元中的分支指令时，确定分支已经被错误预测，或者如果未被检测到被采取的分支，则断言JEClear信号以刷新指令获取单元，并且解码器部分，并将指令指针更改为实际目标地址。在无序部分中，分支指令之前的指令被允许继续执行，并进行到订单退休。同时，在实际目标地址处获取的指令被解码，但是在分支指令已经从无序部分退出之前不允许发出指令，之后清除无序部分内的所有指令，以及则解码指令被允许从解码器发出。状态恢复方法有利地提供了处理器时间的有效利用。

59. 发明授权

US5768576A Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor 失效
标题翻译：用于预测和处理计算机处理器中的子程序指令的解析返回的方法和装置
公开(公告)号：US5768576A
公开(公告)日：1998-06-16
申请号：US739743
申请日：1996-10-29
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/4426
摘要： A method and apparatus for resolving Return From Subroutine instructions in a computer processor are disclosed. The method and apparatus resolve Return From Subroutine instructions in four stages. A first stage predicts Call Subroutine instructions and Return From Subroutine instructions within the instruction stream. The first stage stores a return address in a return register when a Call Subroutine instruction is predicted. The first stage predicts a return to the return address in the return register when a Return From Subroutine instruction is predicted. A second stage decodes each Call Subroutine and Return From Subroutine instruction in order to maintain a Return Stack Buffer that stores a stack of return addresses. Each time the second stage decodes a Call Subroutine instruction, a return address is pushed onto the Return Stack Buffer. Correspondingly, each time the second stage decodes a Return From Subroutine instruction, a return address is popped off of the Return Stack Buffer. The second stage verifies predictions made by the first stage and predicts return addresses for Return From Subroutine instructions that were not predicted by the first stage. A third stage executes Return From Subroutine instructions such that the predictions are verified. Finally, a fourth stage retires Return From Subroutine instructions and ensures that no instructions fetch after a mispredicted return address are committed into permanent state.
摘要翻译：公开了一种用于解决计算机处理器中的子程序返回指令的方法和装置。该方法和设备分四个阶段解析子程序指令。第一阶段预测指令流中的调用子程序指令和子程序返回指令。当预测一个调用子程序指令时，第一阶段将返回地址存储在一个返回寄存器中。第一阶段预测当返回从子程序指令被预测时返回寄存器中的返回地址。第二阶段解码每个调用子程序和从子程序返回指令，以便维护一个存储一堆返回地址的返回栈缓冲区。每次第二阶段解码一个调用子程序指令时，一个返回地址被推到返回栈缓冲区上。相应地，每次第二级解码从子程序返回指令时，返回地址从返回堆栈缓冲区中弹出。第二阶段验证第一阶段做出的预测，并预测第一阶段未预测的返回从子程序指令的返回地址。第三阶段执行从子程序返回指令，使得预测得到验证。最后，第四阶段退出从子程序返回指令，并确保在错误预测的返回地址之后没有指令提取到永久状态。

60. 发明授权

US5812839A Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit 失效
标题翻译：双预测分支系统具有分支恢复过程的两个步骤，仅在错误预测分支是无序单元中最旧的指令时激活
公开(公告)号：US5812839A
公开(公告)日：1998-09-22
申请号：US851141
申请日：1997-05-05
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3844 , G06F9/3863 , G06F9/3885
摘要： A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.
摘要翻译：公开了一种用于流水线处理器的四级分支指令解析系统。分支指令解析系统的第一阶段预测指令流内分支指令的存在和结果，使得指令获取单元可以连续地获取指令。第二阶段解码所有提取的指令。如果解码级确定由第一级预测的分支指令不是分支指令，则解码级别刷新流水线并以校正的地址重新启动处理器。解码阶段验证分支预测阶段所做的所有分支预测。最后，解码阶段对分支预测阶段未预测的分支进行分支预测。第三阶段执行所有分支指令以确定最终分支结果和最终分支目标地址。分支执行阶段将最终分支结果和最终分支目标地址与预测的分支结果和预测分支目标地址进行比较，以确定处理器是否必须冲洗微处理器流水线的前端并以修正的地址重新启动。最终的分支解决阶段退出所有分支指令。退休阶段确保在错误预测的分支之后提取的任何指令不会被永久保留。

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