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51. 发明授权

US5654652A High-speed ratio CMOS logic structure with static and dynamic pullups and/or pulldowns using feedback 失效
标题翻译：具有静态和动态上拉和/或下拉使用反馈的高速比CMOS逻辑结构
公开(公告)号：US5654652A
公开(公告)日：1997-08-05
申请号：US534358
申请日：1995-09-27
申请人： S. Babar Raza , Hagop Nazarian
发明人： S. Babar Raza , Hagop Nazarian
IPC分类号： H03K19/003 , H03K19/017 , H03K19/0948
CPC分类号： H03K19/00361
摘要： A high speed ratio CMOS logic structure includes a static PMOS pullup transistor connected to an output node, and a plurality of NMOS pulldown transistors, connected in parallel, to the output node and which collectively define a pulldown circuit. The pullup transistor is biased using a reference voltage to define a static pullup strength for the logic structure. The pulldown strength of the pulldown circuit is also fixed. The combination of the pullup transistor, and the pulldown transistors define an N input NOR gate. The logic structure, however, further includes a feedback logic circuit, formed by a pair of inverters connected in series coupled to the output node to sense a current logic state of the output node. The feedback logic circuit generates an enable signal that is provided to a second, dynamic PMOS transistor connected in parallel with the static pullup PMOS transistor. When the logic state on the output node is low, the feedback logic circuit generates a low signal, which activates the dynamic PMOS transistor into a conductive state, thus increasing the pullup strength of the logic structure. This increased pullup strength provides for an improved switching for the next logic state transition: low-to-high. Once the output node has transitioned to the logic high state, and after a fixed time delay, the feedback logic circuit generates a logic high signal, which turns off the dynamic PMOS transistor, which weakens the pullup strength of the logic structure. In view of this weakened pullup strength, the next logic state transition of the output node--high-to-low--is accomplished much faster.
摘要翻译：高速比CMOS逻辑结构包括连接到输出节点的静态PMOS上拉晶体管和并联连接到输出节点并且共同定义下拉电路的多个NMOS下拉晶体管。使用参考电压对上拉晶体管进行偏置，以定义逻辑结构的静态上拉强度。下拉电路的下拉强度也是固定的。上拉晶体管和下拉晶体管的组合限定了N个输入NOR门。然而，逻辑结构还包括反馈逻辑电路，其由串联耦合到输出节点的一对反相器形成，以感测输出节点的当前逻辑状态。反馈逻辑电路产生提供给与静态上拉PMOS晶体管并联连接的第二动态PMOS晶体管的使能信号。当输出节点上的逻辑状态为低电平时，反馈逻辑电路产生一个低电平信号，这个信号将动态PMOS晶体管激活成导通状态，从而增加了逻辑结构的上拉电阻。这种增加的上拉强度为下一个逻辑状态转换提供了一个改进的切换：从低到高。一旦输出节点转变到逻辑高电平状态，并且在固定的时间延迟之后，反馈逻辑电路产生逻辑高电平信号，这将关闭动态PMOS晶体管，这削弱了逻辑结构的上拉电阻。鉴于这种上拉强度的削弱，输出节点的下一个逻辑状态转换 - 从高到低实现得快得多。

52. 发明授权

US5467029A OR array architecture for a programmable logic device 失效
标题翻译： OR阵列架构可编程逻辑器件
公开(公告)号：US5467029A
公开(公告)日：1995-11-14
申请号：US144663
申请日：1993-10-28
申请人： Norman P. Taffe , Stephen M. Douglass , Hagop Nazarian
发明人： Norman P. Taffe , Stephen M. Douglass , Hagop Nazarian
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17708
摘要： An OR array including a first multiplicity of OR devices, to which a second multiplicity of product term signals are variably distributed. Some product term signals are distributed to four OR devices, other product term signals are distributed two or three OR devices, and still other product term signals are distributed to only one OR device.
摘要翻译：包括第一多个OR器件的OR阵列，第二多个乘积项信号被可变地分布到该OR器件。一些产品术语信号分配到四个OR设备，其他产品术语信号分配两个或三个OR设备，而其他产品术语信号仅分发给一个OR设备。

53. 发明授权

US08832408B2 Non-volatile memory array partitioning architecture and method to utilize single level cells and multi-level cells within the same memory 有权
标题翻译：非易失性存储器阵列分区体系结构和方法利用同一个存储器内的单级单元和多级单元
公开(公告)号：US08832408B2
公开(公告)日：2014-09-09
申请号：US11928865
申请日：2007-10-30
申请人： Hagop Nazarian , Ali Pourkeramati
发明人： Hagop Nazarian , Ali Pourkeramati
IPC分类号： G06F12/00 , G11C16/08 , G11C11/56
CPC分类号： G11C11/5621 , G11C16/08 , G11C2211/5641
摘要： A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode.
摘要翻译：公开了一种存储器件，并且包括存储器单元阵列和配置成以单级单元模式寻址阵列的第一部分的分区系统，以及以多级单元模式的阵列的第二部分。

54. 发明授权

US08404553B2 Disturb-resistant non-volatile memory device and method 有权
标题翻译：抗干扰的非易失性存储器件及方法
公开(公告)号：US08404553B2
公开(公告)日：2013-03-26
申请号：US12861666
申请日：2010-08-23
申请人： Scott Brad Herner , Hagop Nazarian
发明人： Scott Brad Herner , Hagop Nazarian
IPC分类号： H01L21/20
CPC分类号： H01L27/2463 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1253 , H01L45/14 , H01L45/148 , H01L45/1608 , H01L45/1675
摘要： A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction. The first strip of switching material, the second strip of switching material, the contact material, and the first wiring material are subjected to a second patterning and etching process to form at least a first switching element from the first strip of switching material and at least a second switching element from the second strip of switching material, and a first wiring structure comprising at least the first wiring material and the contact material. The first wiring structure being is in a second direction at an angle to the first direction.
摘要翻译：一种形成抗干扰非易失性存储器件的方法。该方法包括提供具有表面区域并形成覆盖表面区域的第一电介质材料的半导体衬底。第一布线材料覆盖在第一介电材料上，掺杂多晶硅材料覆盖在第一布线材料上，非晶硅开关材料覆盖在所述多晶硅材料上。对开关材料进行第一图案化和蚀刻工艺，以将第一条开关材料与在第一方向上空间取向的第二开关条分离。第一切换材料条，第二条切换材料，接触材料和第一布线材料经受第二图案化和蚀刻工艺，以从第一条开关材料形成至少第一开关元件，并且至少来自所述第二开关材料条的第二开关元件，以及至少包括所述第一布线材料和所述接触材料的第一布线结构。第一布线结构处于与第一方向成一定角度的第二方向。

55. 发明申请

US20120327701A1 MEMORY ARRAY ARCHITECTURE WITH TWO-TERMINAL MEMORY CELLS 有权
标题翻译：具有两个终端记忆细胞的记忆阵列结构
公开(公告)号：US20120327701A1
公开(公告)日：2012-12-27
申请号：US13529985
申请日：2012-06-21
申请人： Hagop Nazarian
发明人： Hagop Nazarian
IPC分类号： H01L47/00 , G11C11/00
CPC分类号： G11C11/1659 , G11C8/14 , G11C11/1653 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2213/33 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2213/82 , H01L27/228 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/148
摘要： A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.
摘要翻译：非易失性存储器件包括沿着第一方向延伸的字线; 沿第二方向延伸的位线; 具有耦合到位线的读取晶体管，至少一个两端存储单元和选择晶体管的存储单元，所述双端存储单元具有耦合到字线的第一端和耦合到栅极的第二端的读取晶体管。双端存储单元的第二端耦合到由选择晶体管的漏极和读取晶体管的栅极共享的公共节点。

56. 发明授权

US08296626B2 Error correction for flash memory 有权
标题翻译：闪存的错误更正
公开(公告)号：US08296626B2
公开(公告)日：2012-10-23
申请号：US12267017
申请日：2008-11-07
申请人： Hagop Nazarian , Ping Hou
发明人： Hagop Nazarian , Ping Hou
IPC分类号： G11C29/00
CPC分类号： G06F11/1072 , G11C2029/0411
摘要： Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.
摘要翻译：本文描述了提供电子存储器的单位和多位纠错。作为示例，可以通过在一组分析的存储器单元的位级分布之间建立可疑区域来实现纠错。可疑区域可以定义分布的潜在错误位。如果对于分布检测到位错误，则可以首先将错误校正应用于可疑区域中的潜在错误位。通过识别怀疑的错误位并将初始误差修正限制在这种识别的位上，可以减轻或避免对分布的所有位应用纠错所涉及的复杂性，从而提高电子存储器误码校正的效率。

57. 发明申请

US20120087169A1 CIRCUIT FOR CONCURRENT READ OPERATION AND METHOD THEREFOR 有权
标题翻译：用于同时读取操作的电路及其方法
公开(公告)号：US20120087169A1
公开(公告)日：2012-04-12
申请号：US12900232
申请日：2010-10-07
申请人： Harry Kuo , Hagop Nazarian
发明人： Harry Kuo , Hagop Nazarian
IPC分类号： G11C7/06 , G11C11/21 , G11C5/06
CPC分类号： G11C13/0004 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C2207/005 , G11C2213/15 , G11C2213/78
摘要： A non-volatile memory device includes a plurality of memory units provided in an array, each memory unit having a plurality of resistive memory cells and a local word line. Each resistive memory units has a first end and a second end, the second ends of the resistive memory cells of each memory unit being coupled to the local word line of the corresponding memory unit. A plurality of bit lines is provided, each bit line being coupled to the first end of one of the resistive memory cells. A plurality of select transistors is provided, each select transistor being assigned to one of the memory units and having a drain terminal coupled to the local word line of the assigned memory unit. First and second global word lines are provided, each global word line being coupled to a control terminal of at least one select transistor. First and second source lines are provided, each source line being coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all of the resistive memory cells in one of the memory units selected for a read operation.
摘要翻译：非易失性存储器件包括设置在阵列中的多个存储器单元，每个存储器单元具有多个电阻存储器单元和本地字线。每个电阻式存储器单元具有第一端和第二端，每个存储器单元的电阻性存储单元的第二端耦合到相应的存储器单元的本地字线。提供多个位线，每个位线耦合到一个电阻存储单元的第一端。提供多个选择晶体管，每个选择晶体管被分配给存储器单元中的一个并且具有耦合到所分配的存储器单元的本地字线的漏极端子。提供第一和第二全局字线，每个全局字线耦合到至少一个选择晶体管的控制端。提供第一和第二源极线，每个源极线耦合到至少一个选择晶体管的源极端子。存储器件被配置为同时读出为读操作选择的存储器单元之一中的所有电阻存储器单元。

58. 发明授权

US08134853B2 High read speed electronic memory with serial array transistors 有权
标题翻译：具有串行阵列晶体管的高速读数电子存储器
公开(公告)号：US08134853B2
公开(公告)日：2012-03-13
申请号：US12642162
申请日：2009-12-18
申请人： Richard Fastow , Hagop Nazarian
发明人： Richard Fastow , Hagop Nazarian
IPC分类号： G11C5/06 , G11C7/06 , H01L21/336
CPC分类号： G11C16/24 , G11C16/26
摘要： Providing a serial array semiconductor architecture achieving fast program, erase and read times is disclosed herein. By way of example, a memory architecture can comprise a serial array of semiconductors coupled to a metal bitline of an electronic memory device at one end of the array, and a gate of a pass transistor at an opposite end of the array. Furthermore, a second metal bitline is coupled to a drain of the pass transistor. A sensing circuit that measures current or voltage at the second metal bitline, which is modulated by a gate potential of the pass transistor, can determine a state of transistors of the serial array. Because of low capacitance of the pass transistor, the serial array can charge or discharge the gate of the pass transistor quickly, resulting in read times that are significantly reduced as compared with conventional serial semiconductor array devices.
摘要翻译：本文公开了提供实现快速编程，擦除和读取时间的串行阵列半导体架构。作为示例，存储器架构可以包括耦合到阵列的一端处的电子存储器件的金属位线的半导体串联阵列，以及位于阵列的相对端的传输晶体管的栅极。此外，第二金属位线耦合到传输晶体管的漏极。测量由通过晶体管的栅极电位调制的第二金属位线处的电流或电压的感测电路可以确定串联阵列的晶体管的状态。由于传输晶体管的低电容，串行阵列可以快速地对传输晶体管的栅极进行充电或放电，导致与常规串行半导体阵列器件相比显着减少的读取时间。

59. 发明申请

US20110305064A1 INTERFACE CONTROL FOR IMPROVED SWITCHING IN RRAM 有权
标题翻译：接口控制改进RRAM中的切换
公开(公告)号：US20110305064A1
公开(公告)日：2011-12-15
申请号：US12814410
申请日：2010-06-11
申请人： Sung Hyun JO , Hagop Nazarian , Wei Lu
发明人： Sung Hyun JO , Hagop Nazarian , Wei Lu
IPC分类号： G11C11/00 , H01L21/02 , H01L45/00
CPC分类号： H01L45/1608 , G11C13/0002 , G11C2213/33 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/148
摘要： A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell.
摘要翻译：存储器件具有包括沿着第一方向延伸的第一电极的第一阵列的交叉开关阵列。第二电极阵列沿第二方向延伸。在由第一阵列和第二阵列限定的交点处在第一电极和第二电极之间提供的非晶硅结构。非晶硅结构具有具有第一缺陷密度的第一层和具有与第一缺陷密度不同的第二缺陷密度的第二层。第一阵列和第二阵列的每个交点定义两端存储单元。

60. 发明授权

US08040738B2 Method and apparatus for performing semiconductor memory operations 有权
标题翻译：用于执行半导体存储器操作的方法和装置
公开(公告)号：US08040738B2
公开(公告)日：2011-10-18
申请号：US12346699
申请日：2008-12-30
申请人： Hagop Nazarian , Imran Khan , Chieu-Yin Chia
发明人： Hagop Nazarian , Imran Khan , Chieu-Yin Chia
IPC分类号： G11C11/34
CPC分类号： G11C16/24 , G11C16/26 , G11C16/3454
摘要： A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging bitlines of the plurality of predetermined memory arrays, performs the memory operation on selected memory cells in the one or more of the plurality of predetermined memory arrays in accordance with the memory operation signal. The bitline decoder includes a plurality of sector select transistors and determines selected ones of the plurality of predetermined memory arrays and selected rows and unselected rows within the selected ones of the plurality of predetermined memory arrays in response to the memory operation signal. The bitline decoder also precharges the bitlines of the plurality of predetermined memory arrays to a first voltage potential then shuts off the sector select transistors of unselected ones of the plurality of predetermined memory arrays and the unselected rows of the selected ones of the plurality of predetermined memory arrays while maintaining the sector select transistors of the selected rows of the selected ones of the plurality of predetermined memory arrays at the first voltage potential prior to the controller performing the memory operation.
摘要翻译：提供半导体存储器件和用于在半导体存储器件中执行存储器操作的方法。半导体存储器件包括多个预定存储器阵列，位线解码器和控制器。控制器向位线解码器提供存储器操作信号，并且在预充电多个预定存储器阵列的位线之后，根据存储器操作对多个预定存储器阵列中的一个或多个存储器单元中的选定存储单元执行存储器操作信号。位线解码器包括多个扇区选择晶体管，并且响应于存储器操作信号确定多个预定存储器阵列中的选定的行以及多个预定存储器阵列中的选定行中的选定行和未选择的行。位线解码器还将多个预定存储器阵列的位线预先充电到第一电压电位，然后关闭多个预定存储器阵列中未选择的存储器阵列的扇区选择晶体管和多个预定存储器中的所选择的存储器的未选择的行阵列，同时在所述控制器执行所述存储器操作之前，将所述多个预定存储器阵列中的选定行的选定行的扇区选择晶体管保持在所述第一电压电位。

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