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51. 发明申请

US20050245035A1 Method for producing low defect density strained -Si channel MOSFETS 有权
标题翻译：低缺陷密度应变-Si沟道MOSFET的制造方法
公开(公告)号：US20050245035A1
公开(公告)日：2005-11-03
申请号：US10838721
申请日：2004-05-03
申请人： Kuen-Chyr Lee , Liang-Gi Yao , Shih-Chang Chen , Mong-Song Liang
发明人： Kuen-Chyr Lee , Liang-Gi Yao , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/20 , H01L21/205 , H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L29/665 , H01L29/78
摘要： A silicon strained channel MOSFET device and method for forming the same the method providing improved wafer throughput and low defect density including the steps of providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane, trisilane, dichlorosilane, and silane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane, trisilane, dichlorosilane, and silane.
摘要翻译：一种硅应变通道MOSFET器件及其形成方法，该方法提供提供晶片生产能力和低缺陷密度的方法，包括提供硅衬底的步骤; 使用选自乙硅烷，丙硅烷，二氯硅烷和硅烷的至少一种沉积前体外延生长第一硅层; 使用选自乙硅烷和丙硅烷的至少一种沉积前体外延生长阶梯级SiGe缓冲层并使第一硅层接触; 使用至少一种选自乙硅烷和丙硅烷的沉积前体外延生长SiGe覆盖层并使其与阶级SiGe缓冲层接触; 并且使用至少一种选自乙硅烷，丙硅烷，二氯硅烷和硅烷的沉积前体外延生长第二硅层。

52. 发明申请

US20050176229A1 NOVEL DEPOSITION METHOD FOR SI-GE EPI LAYER ON DIFFERENT INTERMEDIATE SUBSTRATES 有权
标题翻译：在不同中间基板上的SI-GE EPI层的新型沉积方法
公开(公告)号：US20050176229A1
公开(公告)日：2005-08-11
申请号：US10772939
申请日：2004-02-05
申请人： Liang-Gi Yao , Kuen-Chyr Lee , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Kuen-Chyr Lee , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/331
CPC分类号： H01L29/66242 , H01L21/02532 , H01L21/02579 , H01L21/0262 , Y10S438/918
摘要： A method of forming an Si—Ge epitaxial layer comprising the following steps. A structure is provided and a doped Si—Ge seed layer is formed thereover. The doped Si—Ge seed layer having increased nucleation sites. A Si—Ge epitaxial layer upon the doped Si—Ge seed layer whereby the Si—Ge epitaxial layer lacks discontinuity.
摘要翻译：一种形成Si-Ge外延层的方法，包括以下步骤。提供一种结构，并在其上形成掺杂的Si-Ge种子层。掺杂的Si-Ge种子层具有增加的成核位点。在掺杂Si-Ge晶种层上的Si-Ge外延层，由此Si-Ge外延层缺少不连续性。

53. 发明申请

US20050121671A1 Method for fabricating laminated silicon gate electrode 有权
公开(公告)号：US20050121671A1
公开(公告)日：2005-06-09
申请号：US11041178
申请日：2005-01-24
申请人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
发明人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/20 , H01L21/28 , H01L21/30 , H01L29/49 , H01L29/78 , H01L29/04 , H01L29/10 , H01L31/036 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/02532 , H01L21/02595 , H01L21/2022 , H01L21/28035 , H01L21/3003 , H01L29/4925 , H01L29/78
摘要： Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance.

54. 发明申请

US20050106863A1 Semiconductor wafer manufacturing methods employing cleaning delay period 有权
公开(公告)号：US20050106863A1
公开(公告)日：2005-05-19
申请号：US10712460
申请日：2003-11-13
申请人： Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/00 , H01L21/02 , H01L21/44
CPC分类号： H01L21/02052 , Y10S438/906
摘要： A method of manufacturing a semiconductor wafer including cleaning a surface of the wafer during a first time period and forming a layer over the surface during a second time period. The first time period includes a cleaning delay period prior to a cleaning portion of the first time period, the cleaning delay period configured such that an end time of the first time period substantially coincides with a start time of the second time period.

55. 发明授权

US06649535B1 Method for ultra-thin gate oxide growth 有权
标题翻译：超薄栅极氧化物生长方法
公开(公告)号：US06649535B1
公开(公告)日：2003-11-18
申请号：US10074928
申请日：2002-02-12
申请人： Mo-Chiun Yu , Shih-Chang Chen
发明人： Mo-Chiun Yu , Shih-Chang Chen
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , H01L21/02238 , H01L21/02255 , H01L21/02307 , H01L21/02312 , H01L21/31662
摘要： A method for forming an ultra-thin (between about 15 to 20 Angstroms), silicon dioxide gate insulator layer, featuring a process sequence which widens the process window of the thermal oxidation procedure, and improves the quality of the ultra-thin silicon dioxide gate insulator layer, has been developed. After a series of wet clean procedures applied to a semiconductor substrate, a high temperature anneal procedure is performed in an inert ambient. The high temperature anneal removes organic, as well as inorganic material not removed during the wet clean procedures, and also removes native oxide formed during these same wet clean procedures. The removal of these materials allow the use of longer thermal oxidation times still resulting in silicon dioxide thickness equal to counterparts formed using shorter oxidation times, which were not subjected to the pre-oxidation high temperature anneal procedure. In addition to the widening of the process window, or the use of extended oxidation times, allowed the use of higher oxidation temperatures, resulting in silicon dioxide gate insulator layers exhibiting higher dielectric quality than counterparts formed using lower oxidation temperatures.
摘要翻译：一种用于形成超薄（约15至20埃）的二氧化硅栅极绝缘体层的方法，其特征在于扩大热氧化程序的工艺窗口的工艺顺序，并且提高超薄二氧化硅栅极的质量绝缘子层，已经开发。在对半导体衬底施加一系列湿法清洁程序之后，在惰性环境中进行高温退火程序。高温退火除去有机物以及在湿法清洁过程中未除去的无机材料，还可以除去在这些相同的湿法清洗过程中形成的天然氧化物。这些材料的去除允许使用更长的热氧化时间，仍然导致二氧化硅厚度等于不经过预氧化高温退火工艺的较短氧化时间形成的对应物。除了扩大工艺窗口，或者使用延长的氧化时间，允许使用更高的氧化温度，导致比使用较低氧化温度形成的对应物质更高的介电质量的二氧化硅栅极绝缘体层。

56. 发明授权

US06495422B1 Methods of forming high-k gate dielectrics and I/O gate oxides for advanced logic application 有权
标题翻译：形成高k栅极电介质和I / O栅极氧化物的方法用于高级逻辑应用
公开(公告)号：US06495422B1
公开(公告)日：2002-12-17
申请号：US10035552
申请日：2001-11-09
申请人： Mo-Chiun Yu , Shih-Chang Chen
发明人： Mo-Chiun Yu , Shih-Chang Chen
IPC分类号： H01L218234
CPC分类号： H01L21/28202 , H01L21/823462 , H01L21/823481 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of simultaneously forming a high-k metal oxide dielectric layer and a gate oxide dielectric layer comprising the following steps. A structure having isolation regions which separate the structure into at least one core device active region and one I/O active region is provided. A buffer layer is formed over the structure and the isolation regions. A metal containing layer is formed over the buffer layer. The metal containing layer and the buffer layer are patterned to: form an exposed patterned metal containing layer within the at least one core device action region; and expose the structure within the at least one I/O active region. The exposed patterned metal containing layer and the exposed structure within the at least one I/O active region are oxidized to simultaneously form: the high-k metal oxide dielectric layer within the at least one core device active region; and the gate oxide dielectric layer within the at least one I/O active region.
摘要翻译：一种同时形成高k金属氧化物电介质层和栅极氧化物电介质层的方法，包括以下步骤。提供具有将结构分离成至少一个核心器件有源区和一个I / O有源区的隔离区的结构。在结构和隔离区上形成缓冲层。在缓冲层上形成含金属层。图案化含金属层和缓冲层以在至少一个核心器件作用区域内形成暴露图案化的含金属层; 以及暴露所述至少一个I / O活动区域内的结构。曝光的图案化的金属含有层和暴露的结构在至少一个I / O有源区内被氧化，同时形成：至少一个核心器件有源区内的高k金属氧化物介电层; 以及所述至少一个I / O有源区内的栅极氧化物介电层。

57. 发明申请

US20140029295A1 HYBRID LIGHT GUIDE PLATE AND DISPLAY DEVICE 有权
标题翻译：混合光导板和显示设备
公开(公告)号：US20140029295A1
公开(公告)日：2014-01-30
申请号：US13951468
申请日：2013-07-26
申请人： Chun-Chung Hsiao , Shih-Chang Chen , Cheng-Tsung Li , Tzeng-Ke Shiau
发明人： Chun-Chung Hsiao , Shih-Chang Chen , Cheng-Tsung Li , Tzeng-Ke Shiau
IPC分类号： F21V8/00
CPC分类号： G02B6/0011 , G02B6/0043 , G02B6/005 , G02B6/0088 , G02F1/133308 , G02F1/133615 , G02F2001/133317
摘要： A display device includes a housing, a frame bonded to the housing, and a display module. The display module includes a back cover bonded to the frame, a light guide plate (LGP), a support element, a display panel, and an optical film set. The LGP is supported on the back cover and has a light exiting surface and an opposite back surface. At least two sides of the LGP's back surface are adhered on the back cover, and the LGP is made of glass. The support element and display panel are supported respectively on the LGP and support element. The optical film set is between the display panel and LGP. A hybrid LGP includes a first light guide sub-plates and a second light guide sub-plate. The second light guide sub-plate is stacked on and bonded to the first light guide sub-plate.
摘要翻译：显示装置包括壳体，结合到壳体的框架和显示模块。显示模块包括接合到框架的后盖，导光板（LGP），支撑元件，显示面板和光学膜组。 LGP支撑在后盖上，并具有光出射表面和相对的后表面。 LGP的后表面的至少两侧粘附在后盖上，LGP由玻璃制成。支撑元件和显示面板分别支撑在LGP和支撑元件上。光学胶片组在显示面板和LGP之间。混合式LGP包括第一导光子板和第二导光子板。第二导光子板堆叠在第一导光子板上并结合到第一导光子板上。

58. 发明授权

US08564018B2 Relaxed silicon germanium substrate with low defect density 有权
标题翻译：具有低缺陷密度的松弛硅锗衬底
公开(公告)号：US08564018B2
公开(公告)日：2013-10-22
申请号：US12038091
申请日：2008-02-27
申请人： Chun Chich Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
发明人： Chun Chich Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
IPC分类号： H01L21/02
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/324
摘要： A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.
摘要翻译：公开了一种用于集成电路的结构。该结构包括晶体衬底和四个结晶层。第一晶格常数的第一晶体层位于晶体衬底上。第二晶体层具有不同于第一晶格常数的第二晶格常数，并且位于所述第一晶体层上。第三晶体层具有与所述第二晶格常数不同的第三晶格常数，并且位于所述第二晶体层上。应变的第四晶体层至少部分地包括MOSFET器件。

59. 发明授权

US08557669B2 MOSFET device with localized stressor 有权
标题翻译：具有局部应力源的MOSFET器件
公开(公告)号：US08557669B2
公开(公告)日：2013-10-15
申请号：US12176655
申请日：2008-07-21
申请人： Chien-Hao Chen , Pang-Yen Tsai , Chie-Chien Chang , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Pang-Yen Tsai , Chie-Chien Chang , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/42
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/823807 , H01L29/165 , H01L29/45 , H01L29/517 , H01L29/518 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.
摘要翻译：提供具有局部应力的MOSFET。 MOSFET具有形成在源极/漏极区域中的应力诱导层，其中应力诱导层包括第一半导体材料和第二半导体材料。对应力诱导层进行处理，使得由第一半导体材料引起反应，并且第二半导体材料被迫下降到应力诱导层中。应力诱导层可以是凹陷区域或非凹陷区域。第一种方法包括在源极/漏极区域中形成诸如SiGe的应力诱导层并进行氮化或氧化过程。在应力诱导层的顶部形成氮化物或氧化物膜，迫使Ge较低进入应力诱导层。另一方法实施例涉及在应力诱导层上形成反应层，并进行处理工艺以使反应层与应力诱导层反应。

60. 发明授权

US08222136B2 Method of forming contacts for a semiconductor device 有权
标题翻译：形成半导体器件的触点的方法
公开(公告)号：US08222136B2
公开(公告)日：2012-07-17
申请号：US12906868
申请日：2010-10-18
申请人： Yuan-Tien Tu , Tsai-Chun Li , Huan-Just Lin , Shih-Chang Chen
发明人： Yuan-Tien Tu , Tsai-Chun Li , Huan-Just Lin , Shih-Chang Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76816
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成层。所述方法包括在所述层中形成暴露所述衬底的第一区域的第一开口。该方法包括通过第一溅射工艺去除在第一区域上形成的第一氧化层。该方法包括用导电材料填充第一开口。所述方法包括在所述层中形成暴露所述衬底的第二区域的第二开口，所述第二区域不同于所述第一区域。该方法包括通过第二溅射工艺除去在第二区域上形成的第二氧化层。第一和第二溅射工艺之一比另一个更强大。

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