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51. 发明授权

US5060230A On chip semiconductor memory arbitrary pattern, parallel test apparatus and method 失效
标题翻译：芯片半导体存储器仲裁模式，并行测试装置和方法
公开(公告)号：US5060230A
公开(公告)日：1991-10-22
申请号：US400899
申请日：1989-08-30
申请人： Kazutami Arimoto , Kazuyasu Fujishima , Yoshio Matsuda , Tsukasa Ooishi , Masaki Tsukude
发明人： Kazutami Arimoto , Kazuyasu Fujishima , Yoshio Matsuda , Tsukasa Ooishi , Masaki Tsukude
IPC分类号： G06F11/267 , G11C29/00 , G11C29/12 , G11C29/34
CPC分类号： G11C29/78 , G11C29/12 , G11C29/34 , G06F11/267
摘要： An apparatus for parallel testing of a semiconductor memory with arbitrary data patterns and capable of being integrated on the memory chip. The semiconductor memory test device in a preferred embodiment is compatible with hierarchical data bus lines including an input/output line pair (I/O, I/O), a plurality of sub-input/output line pairs (SIO1SIO1; SIO2, SIO2) and a plurality of bit line pairs (BL1, BL1; BL6, BL6). A plurality of comparators (50) and a plurality of registers (60) are provided corresponding to a plurality of sub-input/output line pairs (SIO1, SIO2; SIO2, SIO2). The plurality of registers (50) which also functions as intermediated output amplifiers can hold random data applied through the input/output line pair (I/O, I/O). The plurality of comparators (60) is provided to determine whether or not data read out onto a plurality of sub-input/output line pairs (SIO1, SIO1; SIO2, SIO2) from a row of memory cells (MC1, MC2) corresponding to a single word line (WL) match respective data held in the plurality of registers (60).
摘要翻译：一种用于并行测试具有任意数据模式并能够集成在存储器芯片上的半导体存储器的装置。优选实施例中的半导体存储器测试装置与包括输入/输出线对（I / O，I / O），多个子输入/输出线对（SIO1 + L，SIO1; SIO2，SIO2）和多个位线对（BL1，BL1; BL6，BL6）。对应于多个子输入/输出线对（SIO1，SIO2; SIO2，SIO2）提供多个比较器（50）和多个寄存器（60）。也可以用作中间输出放大器的多个寄存器（50）可以保存通过输入/输出线对（I / O，I / O）施加的随机数据。多个比较器（60）被提供以确定从对应于存储单元（MC1，MC2）的一行的多个子输入/输出线对（SIO1，SIO1; SIO2，SIO2）单个字线（WL）匹配保存在多个寄存器（60）中的相应数据。

52. 发明授权

US5682343A Hierarchical bit line arrangement in a semiconductor memory 失效
标题翻译：半导体存储器件中的分层位线布置
公开(公告)号：US5682343A
公开(公告)日：1997-10-28
申请号：US664886
申请日：1996-06-17
申请人： Shigeki Tomishima , Masaki Tsukude , Mikio Asakura , Kazuyasu Fujishima
发明人： Shigeki Tomishima , Masaki Tsukude , Mikio Asakura , Kazuyasu Fujishima
IPC分类号： G11C11/401 , G11C7/18 , G11C11/4096 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C5/06
CPC分类号： G11C7/18 , G11C11/4096
摘要： Main bit lines MBL and ZMBL are disposed at opposite sides of a sense amplifier SA. Main bit lines MBL and ZMBL each are provided for paired sub-bit lines SBL1 and SBL2 (or SBL3 and SBL4). Sub-bit line pair SBL1 and SBL2 is connected to main bit line MBL via a block select switch T1. Sub-bit line pair SBL3 and SBL4 is connected to main bit line ZMBL via a block select switch T2. Since one main bit line is provided for two sub-bit lines, a pitch of the main bit lines is twice as large as a pitch of the sub-bit lines, so that conditions on the pitch of main bit lines are remarkably eased, which facilitates layout of elements.
摘要翻译：主位线MBL和ZMBL设置在读出放大器SA的相对侧。为配对的子位线SBL1和SBL2（或SBL3和SBL4）提供主位线MBL和ZMBL。子位线对SBL1和SBL2经由块选择开关T1连接到主位线MBL。子位线对SBL3和SBL4通过块选择开关T2连接到主位线ZMBL。由于为两个子位线提供一个主位线，所以主位线的间距是子位线的间距的两倍，使得主位线的间距条件显着地减轻，其中促进元素布局。

53. 发明授权

US06707735B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06707735B2
公开(公告)日：2004-03-16
申请号：US10120445
申请日：2002-04-12
申请人： Ryu Makabe , Masaki Tsukude , Hirotoshi Sato
发明人： Ryu Makabe , Masaki Tsukude , Hirotoshi Sato
IPC分类号： G11C700
CPC分类号： G11C29/46
摘要： When address signal bits and/or data bits in a predetermined pattern are accessed a predetermined number of times successively, a test mode can be set. By using address signal bits and/or data bits as a test command for designating a test content, a test content is specified. A semiconductor memory device with an interface compatible with an interface of a normal static random access memory is provided.
摘要翻译：当预定模式的地址信号位和/或数据位连续访问预定次数时，可以设置测试模式。通过使用地址信号位和/或数据位作为用于指定测试内容的测试命令，指定测试内容。提供具有与普通静态随机存取存储器的接口兼容的接口的半导体存储器件。

54. 发明授权

US06590823B2 Refresh-circuit-containing semiconductor memory device 失效
公开(公告)号：US06590823B2
公开(公告)日：2003-07-08
申请号：US09988172
申请日：2001-11-19
申请人： Masaki Tsukude
发明人： Masaki Tsukude
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A refresh circuit performs directive operation for the execution of refresh operation in response to a cycle signal cyclically output from a timer circuit provided in a command-signal activating circuit. To execute testing, a stop signal generated in response to an external signal is activated, the activated stop signal is input to an AND gate, and the cycle signal is thereby invalidated. This causes the refresh operation to terminate, thereby enabling this semiconductor memory device to refresh characteristic testing to be performed.

55. 发明授权

US06556485B2 Output buffer capable of adjusting current drivability and semiconductor integrated circuit device having the same 失效
公开(公告)号：US06556485B2
公开(公告)日：2003-04-29
申请号：US09972242
申请日：2001-10-09
申请人： Tadayuki Shimizu , Hirotoshi Sato , Masaki Tsukude
发明人： Tadayuki Shimizu , Hirotoshi Sato , Masaki Tsukude
IPC分类号： G11C700
CPC分类号： G11C7/1051
摘要： An output buffer includes first current driving units connected in parallel between a power-supply voltage and an output node; second current driving units connected in parallel between a ground voltage and an output node; a plurality of operation selection circuits setting the respective first and second current driving units to be in either activated or inactivated state in a non-volatile manner; first signal transmission circuits arranged respectively corresponding to the first current driving circuits and each transmitting the level of output data with a similar first propagation time period; and second signal transmission circuits arranged respectively corresponding to the second current driving units and each transmitting the level of the output data with a similar second propagation time period.

56. 发明授权

US6038183A Semiconductor memory device having burn-in mode operation stably accelerated 失效
标题翻译：具有老化模式操作的半导体存储器件稳定地加速
公开(公告)号：US6038183A
公开(公告)日：2000-03-14
申请号：US288019
申请日：1999-04-08
申请人： Masaki Tsukude
发明人： Masaki Tsukude
IPC分类号： G01R31/28 , G01R31/30 , G11C5/00 , G11C11/401 , G11C11/407 , G11C29/06 , G11C7/00
CPC分类号： G11C29/06 , G11C29/12005 , G11C29/26 , G11C29/34 , G11C29/50 , G11C5/00 , G11C11/401 , G11C2029/1202 , G11C2029/2602
摘要： Current is reduced in driving a word line in stress acceleration testing such as burn-in, and the time required for the stress acceleration testing is reduced. For an address signal applied from an address buffer, a predetermined internal address signal bit is degenerated and a remaining address signal bit is rendered valid in response to an activation of a stress acceleration mode designation signal to simultaneously drive a desired number of word lines of all word lines to selected state. Any number of word lines can be simultaneously selected and hence current flowing in driving word lines can be reduced in the stress acceleration mode. In the stress acceleration mode of operation, bit line voltage and cell plate voltage are changed, and a current required for driving a plurality of word lines into a selected state is limited.
摘要翻译：压力加速度测试（如老化）中的字线驱动电流减少，应力加速测试所需的时间减少。对于从地址缓冲器施加的地址信号，预定的内部地址信号位退化，并且剩余地址信号位响应于应力加速模式指定信号的激活而变为有效，以同时驱动所需数量的所有字线字线到选定状态。可以同时选择任何数量的字线，因此在应力加速模式中可以减少在驱动字线中流动的电流。在应力加速操作模式中，位线电压和单元板电压发生变化，并且将多条字线驱动到选定状态所需的电流受到限制。

57. 发明授权

US6011428A Voltage supply circuit and semiconductor device including such circuit 失效
标题翻译：电源电路和包括这种电路的半导体器件
公开(公告)号：US6011428A
公开(公告)日：2000-01-04
申请号：US135650
申请日：1993-10-14
申请人： Masaki Tsukude , Masanori Hayashikoshi
发明人： Masaki Tsukude , Masanori Hayashikoshi
IPC分类号： G05F1/56 , G05F3/24 , G11C5/14 , G11C11/401 , G11C11/407 , H03K5/003 , G05F1/10
CPC分类号： G05F3/245 , G05F3/24 , G11C5/147 , Y10S323/907
摘要： The level shifter circuit of an internal down converter includes a P channel MOS transistor constituting a resistance component, and a resistor constituting a resistance component. The temperature coefficient of resistance component is set larger than the temperature coefficient of resistance component so that the output voltage of level shifter circuit has a negative temperature characteristic. If a reference voltage generated by reference voltage generation circuit decreases when operating at a high temperature, the output voltage of level shifter circuit decreases as well. Thus, change in an internal voltage due to change in the operation temperature can be compensated.
摘要翻译：内部下变频器的电平移位电路包括构成电阻分量的P沟道MOS晶体管和构成电阻分量的电阻。电阻分量的温度系数设定为大于电阻分量的温度系数，使得电平移位器电路的输出电压具有负温度特性。如果在高温工作时由参考电压产生电路产生的参考电压降低，则电平转换器电路的输出电压也会降低。因此，可以补偿由于操作温度的变化引起的内部电压的变化。

58. 发明授权

US5987619A Input signal phase compensation circuit capable of reliably obtaining external data 失效
标题翻译：能够可靠地获得外部数据的输入信号相位补偿电路
公开(公告)号：US5987619A
公开(公告)日：1999-11-16
申请号：US947372
申请日：1997-10-08
申请人： Takeshi Hamamoto , Masaki Tsukude
发明人： Takeshi Hamamoto , Masaki Tsukude
IPC分类号： G11C11/407 , G06F1/10 , G11C11/409 , G06F1/04
CPC分类号： G06F1/10
摘要： An input signal phase compensation circuit having a monitor mode and a normal operation mode includes a mode switching circuit, a logic gate receiving an internal data signal, a delay circuit connected to the logic gate, and a phase comparator comparing, in the monitor mode, phases of a signal output from the delay circuit and a clock signal, and determining time for delaying an internal clock signal in a variable delay circuit so as to match phases of the both signals. In the normal operation mode, the time is fixed, and data is obtained at phase compensated timing.
摘要翻译：具有监视模式和正常操作模式的输入信号相位补偿电路包括模式切换电路，接收内部数据信号的逻辑门，连接到逻辑门的延迟电路，以及在监视器模式下，从延迟电路输出的信号的相位和时钟信号，以及确定用于延迟可变延迟电路中的内部时钟信号的时间，以便匹配两个信号的相位。在正常工作模式下，时间是固定的，并且在相位补偿定时获得数据。

59. 发明授权

US5982698A Multi-bank system semiconductor memory device capable of operating at high speed 失效
标题翻译：能够高速运转的多存储体系半导体存储器件
公开(公告)号：US5982698A
公开(公告)日：1999-11-09
申请号：US215927
申请日：1998-12-18
申请人： Masaki Tsukude
发明人： Masaki Tsukude
IPC分类号： G11C11/401 , G11C7/06 , G11C8/00 , G11C8/12 , G11C11/407 , G11C11/409
CPC分类号： G11C7/06 , G11C8/12
摘要： A semiconductor integrated circuit device of the present invention includes a plurality of banks and a plurality of sense amplifier bands. A switch circuit included in each sense amplifier band receives a signal on a transmission line and outputs a signal read from the bank to a global data input/output line arranged in the column direction. A column bank control circuit for outputting a column bank control signal is arranged on the column decoder side. The column bank control signal is supplied to the transmission line through a column bank control signal line arranged in the column direction. The switch circuit operates in accordance with the column bank control signal. By such a configuration, a column-related operation can be matched easily.
摘要翻译：本发明的半导体集成电路器件包括多个堤和多个读出放大器带。包括在每个读出放大器带中的开关电路接收传输线上的信号，并将从存储体读出的信号输出到沿列方向布置的全局数据输入/输出线。用于输出列组控制信号的列组控制电路被布置在列解码器侧。列列控制信号通过沿列方向布置的列组控制信号线提供给传输线。开关电路根据列组控制信号进行工作。通过这样的配置，可以容易地匹配列相关操作。

60. 发明授权

US5949731A Semiconductor memory device having burn-in mode operation stably accelerated 失效
公开(公告)号：US5949731A
公开(公告)日：1999-09-07
申请号：US941215
申请日：1997-09-30
申请人： Masaki Tsukude
发明人： Masaki Tsukude
IPC分类号： G01R31/28 , G01R31/30 , G11C5/00 , G11C11/401 , G11C11/407 , G11C29/06 , G11C8/00
CPC分类号： G11C29/06 , G11C29/12005 , G11C29/26 , G11C29/34 , G11C29/50 , G11C5/00 , G11C11/401 , G11C2029/1202 , G11C2029/2602
摘要： Current is reduced in driving a word line in stress acceleration testing such as burn-in, and the time required for the stress acceleration testing is reduced. For an address signal applied from an address buffer, a predetermined internal address signal bit is degenerated and a remaining address signal bit is rendered valid in response to an activation of a stress acceleration mode designation signal to simultaneously drive a desired number of word lines of all word lines to selected state. Any number of word lines can be simultaneously selected and hence current flowing in driving word lines can be reduced in the stress acceleration mode. In the stress acceleration mode of operation, bit line voltage and cell plate voltage are changed, and a current required for driving a plurality of word lines into a selected state is limited.

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