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51. 发明授权

US08569830B2 Semiconductor device having vertical MOS transistor and method for manufacturing the semiconductor device 失效
标题翻译：具有垂直MOS晶体管的半导体器件及其制造方法
公开(公告)号：US08569830B2
公开(公告)日：2013-10-29
申请号：US12230562
申请日：2008-09-02
申请人： Kiyonori Oyu , Yoshihiro Takaishi , Yu Kosuge
发明人： Kiyonori Oyu , Yoshihiro Takaishi , Yu Kosuge
IPC分类号： H01L29/66
CPC分类号： H01L29/66666 , H01L21/823487 , H01L27/10823 , H01L27/10873 , H01L29/4238 , H01L29/7827
摘要： In a vertical MOS transistor in which a semiconductor pillar is formed by etching a semiconductor substrate in a portion surrounded by an isolation film, the semiconductor pillar is covered with a gate insulating film and a gate electrode to be made a channel part, and diffusion layers to be a source and a drain are included on a top and a bottom of the channel part, electrode which controls potential of a gate electrode material is formed in gate electrode material formed on a side surface of isolation film, in order to eliminate a parasitic MOS operation by the gate electrode material remaining on the side surface of the isolation film.
摘要翻译：在通过在由隔离膜包围的部分中蚀刻半导体衬底形成半导体柱的垂直MOS晶体管中，半导体柱被栅绝缘膜和栅电极覆盖以形成沟道部分，扩散层作为源极和漏极包括在沟道部分的顶部和底部，控制栅电极材料的电位的电极形成在形成在隔离膜的侧表面上的栅电极材料中，以消除寄生通过留在隔离膜的侧表面上的栅电极材料进行MOS操作。

52. 发明授权

US07910982B2 Semiconductor apparatus and production method of the same 有权
标题翻译：半导体装置及其制作方法相同
公开(公告)号：US07910982B2
公开(公告)日：2011-03-22
申请号：US12132977
申请日：2008-06-04
申请人： Kiyonori Oyu
发明人： Kiyonori Oyu
IPC分类号： H01L29/66
CPC分类号： H01L29/66787 , H01L21/743 , H01L27/11 , H01L27/1104 , H01L29/0657 , H01L29/66666 , H01L29/7827
摘要： In order to provide a highly integrated semiconductor apparatus and a production method thereof which can avoid the floating of a channel portion that causes a problem when constituting a memory cell from three-dimensional transistors, a semiconductor apparatus includes: multiple three-dimensional transistors each of which includes: a first pillar; a channel portion provided at the first pillar; diffused layers formed at both an upper portion and a lower portion of the channel portion; and a gate electrode provided around the channel portion via a gate insulation film; and a second pillar which is electrically conductive, wherein the multiple three-dimensional transistors are arranged on a well area while surrounding the second pillar, the multiple three dimensional transistors share the second pillar, and the channel portions of the multiple three dimensional transistors are each connected to the second pillar by a channel connection portion. In addition, six three-dimensional transistors preferably share the second pillar which is a single pillar.
摘要翻译：为了提供高度集成的半导体装置及其制造方法，其可以避免在从三维晶体管构成存储单元时引起问题的沟道部分的浮置，半导体装置包括：多个三维晶体管，其中包括：第一支柱; 设置在第一支柱处的通道部分; 形成在通道部分的上部和下部的扩散层; 以及通过栅极绝缘膜设置在所述沟道部分周围的栅电极; 以及导电的第二支柱，其中所述多个三维晶体管布置在阱区上，同时围绕所述第二柱，所述多个三维晶体管共享所述第二柱，并且所述多个三维晶体管的沟道部分各自通过通道连接部连接到第二支柱。此外，六个三维晶体管优选地共享作为单个柱的第二柱。

53. 发明申请

US20100072552A1 FIELD EFFECT TRANSISTOR FOR PREVENTING COLLAPSE OR DEFORMATION OF ACTIVE REGIONS 审中-公开
标题翻译：用于防止活动区域的褶皱或变形的场效应晶体管
公开(公告)号：US20100072552A1
公开(公告)日：2010-03-25
申请号：US12561793
申请日：2009-09-17
申请人： Hideo SUNAMI , Atsushi Sugimura , Kiyoshi Okuyama , Kiyonori Oyu , Hideharu Miyake
发明人： Hideo SUNAMI , Atsushi Sugimura , Kiyoshi Okuyama , Kiyonori Oyu , Hideharu Miyake
IPC分类号： H01L27/105 , H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L27/10823 , H01L27/10873 , H01L27/11507 , H01L29/0657 , H01L29/66666
摘要： A field effect transistor includes an active region provided in a projecting part on a surface of a semiconductor substrate, the projecting part extending in a fixed direction parallel to the surface, and a gate electrode provided on a sidewall of the projecting part along the fixed direction with a gate insulating films interposed.
摘要翻译：场效应晶体管包括设置在半导体衬底的表面上的突出部分中的有源区域，突出部分沿平行于表面的固定方向延伸，以及沿着固定方向设置在突出部分的侧壁上的栅电极插入栅极绝缘膜。

54. 发明授权

US07682895B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07682895B2
公开(公告)日：2010-03-23
申请号：US11678894
申请日：2007-02-26
申请人： Kiyonori Oyu
发明人： Kiyonori Oyu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823892 , H01L21/3221 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： A method of manufacturing a semiconductor device includes: (A) a wafer process; and (B) a bias application process after the wafer process. The wafer process includes: (a) forming a n-type well in a p-type semiconductor substrate; (b) forming a p-type well in the n-type well; and (c) forming a transistor on the p-type well, the transistor having a n-type source/drain diffusion layer. In the bias application process, a forward bias is applied between the p-type well and the n-type well to move heavy metal ions.
摘要翻译：制造半导体器件的方法包括：（A）晶片工艺; 和（B）晶片处理之后的偏置施加处理。晶片工艺包括：（a）在p型半导体衬底中形成n型阱; （b）在n型井中形成p型井; 和（c）在p型阱上形成晶体管，该晶体管具有n型源极/漏极扩散层。在偏压施加过程中，在p型阱和n型阱之间施加正向偏压以移动重金属离子。

55. 发明授权

US07649256B2 Semiconductor chip having pollished and ground bottom surface portions 有权
标题翻译：半导体芯片具有抛物面和底面底面部分
公开(公告)号：US07649256B2
公开(公告)日：2010-01-19
申请号：US11176642
申请日：2005-07-08
申请人： Hiroshi Kujirai , Kiyonori Oyu
发明人： Hiroshi Kujirai , Kiyonori Oyu
IPC分类号： H01L21/30
CPC分类号： H01L21/304 , H01L25/0657 , H01L25/50 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L2924/01078 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor chip having a thickness of 130 micrometers or less includes a mechanically ground bottom surface corresponding to a central circuit area, and a polished bottom surface corresponding to a peripheral scribe area. The mechanically ground bottom surface prevents heavy metals attached onto the bottom surface of the wafer from diffusing toward the source/drain regions of the semiconductor substrate and thereby from degrading the transistor characteristics.
摘要翻译：具有130微米或更小的厚度的半导体芯片包括对应于中心电路区域的机械接地底表面和对应于外围划线区域的抛光底面。机械底部底表面防止附着在晶片的底表面上的重金属向半导体衬底的源极/漏极区扩散，从而降低晶体管特性。

56. 发明申请

US20080303083A1 SEMICONDUCTOR APPARATUS AND PRODUCTION METHOD OF THE SAME 有权
标题翻译：其半导体装置及其生产方法
公开(公告)号：US20080303083A1
公开(公告)日：2008-12-11
申请号：US12132977
申请日：2008-06-04
申请人： Kiyonori Oyu
发明人： Kiyonori Oyu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66787 , H01L21/743 , H01L27/11 , H01L27/1104 , H01L29/0657 , H01L29/66666 , H01L29/7827
摘要： In order to provide a highly integrated semiconductor apparatus and a production method thereof which can avoid the floating of a channel portion that causes a problem when constituting a memory cell from three-dimensional transistors, a semiconductor apparatus includes: multiple three-dimensional transistors each of which includes: a first pillar; a channel portion provided at the first pillar; diffused layers formed at both an upper portion and a lower portion of the channel portion; and a gate electrode provided around the channel portion via a gate insulation film; and a second pillar which is electrically conductive, wherein the multiple three-dimensional transistors are arranged on a well area while surrounding the second pillar, the multiple three dimensional transistors share the second pillar, and the channel portions of the multiple three dimensional transistors are each connected to the second pillar by a channel connection portion. In addition, six three-dimensional transistors preferably share the second pillar which is a single pillar.
摘要翻译：为了提供高度集成的半导体装置及其制造方法，其可以避免在从三维晶体管构成存储单元时引起问题的沟道部分的浮置，半导体装置包括：多个三维晶体管，其中包括：第一支柱; 设置在第一支柱处的通道部分; 形成在通道部分的上部和下部的扩散层; 以及通过栅极绝缘膜设置在所述沟道部分周围的栅电极; 以及导电的第二支柱，其中所述多个三维晶体管布置在阱区上，同时围绕所述第二柱，所述多个三维晶体管共享所述第二柱，并且所述多个三维晶体管的沟道部分各自通过通道连接部连接到第二支柱。此外，六个三维晶体管优选地共享作为单个柱的第二柱。

57. 发明申请

US20060203590A1 Dynamic random access memories and method for testing performance of the same 有权
标题翻译：动态随机存取存储器及其性能测试方法
公开(公告)号：US20060203590A1
公开(公告)日：2006-09-14
申请号：US11341717
申请日：2006-01-30
申请人： Yuki Mori , Renichi Yamada , Shuichi Tsukada , Kiyonori Oyu
发明人： Yuki Mori , Renichi Yamada , Shuichi Tsukada , Kiyonori Oyu
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/401 , G11C29/50016
摘要： The present invention enables screening of the so-called variable retention time (VRT) failure, namely a retention failure occurring in a DRAM due to fluctuation of a data retention time like a random telegraph noise. A pause/refresh test for checking a data retention function is repeated at all memory cells of a chip so that memory cells at which the retention failure due to random fluctuation of the data retention capability over time may occur is subjected to screening.
摘要翻译：本发明能够筛选所谓的可变保留时间（VRT）故障，即由于诸如随机电报噪声的数据保留时间的波动而在DRAM中发生的保留故障。在芯片的所有存储单元上重复用于检查数据保留功能的暂停/刷新测试，使得可能发生由于数据保留能力的随机波动而发生的保留故障的存储单元被进行筛选。

58. 发明申请

US20060125060A1 Semiconductor chip, and manufacturing method and application of the chip 有权
标题翻译：半导体芯片，芯片的制造方法和应用
公开(公告)号：US20060125060A1
公开(公告)日：2006-06-15
申请号：US11290509
申请日：2005-12-01
申请人： Kiyonori Oyu
发明人： Kiyonori Oyu
IPC分类号： H01L23/544
CPC分类号： H01L23/562 , H01L27/105 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/10158 , H01L2924/15311 , H01L2224/0401
摘要： The present invention provides a semiconductor chip that provides a semiconductor device with high reliability and low leak current, and a method of manufacturing such a semiconductor chip, and more specifically, provides a semiconductor chip comprising memory portions and a peripheral circuit portion, where the memory portions and the peripheral circuit portion are formed in a main surface portion of the semiconductor chip, a thickness of the sections of the semiconductor chip passing through the main surface portion in which the memory portions are formed is larger than a thickness of sections of the semiconductor chip passing through the main surface portion in which the peripheral circuit portion is formed, and a method of manufacturing such a semiconductor chip.
摘要翻译：本发明提供一种半导体芯片，其提供具有高可靠性和低漏电流的半导体器件，以及制造这种半导体芯片的方法，更具体地，提供一种包括存储器部分和外围电路部分的半导体芯片，其中存储器部分和外围电路部分形成在半导体芯片的主表面部分中，通过形成存储部分的主表面部分的半导体芯片的部分的厚度大于半导体的部分的厚度芯片通过形成有外围电路部分的主表面部分，以及制造这种半导体芯片的方法。

59. 发明授权

US07057243B2 Hybrid semiconductor device having an n+ (p) doped n-type gate and method of producing the same 有权
标题翻译：具有n +（p）掺杂n型栅极的混合半导体器件及其制造方法
公开(公告)号：US07057243B2
公开(公告)日：2006-06-06
申请号：US10648883
申请日：2003-08-27
申请人： Satoru Yamada , Ryo Nagai , Kiyonori Oyu , Ryoichi Nakamura , Norikatsu Takaura
发明人： Satoru Yamada , Ryo Nagai , Kiyonori Oyu , Ryoichi Nakamura , Norikatsu Takaura
IPC分类号： H01L29/94
CPC分类号： H01L27/10891 , H01L21/28061 , H01L21/823842 , H01L27/10894 , H01L27/10897 , H01L29/4941 , H01L29/7833
摘要： In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.
摘要翻译：在具有三个或更多个不同费米能级的多晶硅栅电极结构的半导体器件中，具有最低费米能级的P型多晶硅设置在第一N型表面沟道MOS晶体管上。具有最高费米能级的第一N型多晶硅被布置在第二N型表面沟道MOS晶体管上。具有最高和最低费米能级之间的中间费米能级并且掺杂有N型杂质和P型杂质的第二N型多晶硅设置在P沟道MOS晶体管上。

60. 发明申请

US20060006528A1 Semiconductor chip having pollished and ground bottom surface portions 有权
标题翻译：半导体芯片具有抛物面和底面底面部分
公开(公告)号：US20060006528A1
公开(公告)日：2006-01-12
申请号：US11176642
申请日：2005-07-08
申请人： Hiroshi Kujirai , Kiyonori Oyu
发明人： Hiroshi Kujirai , Kiyonori Oyu
IPC分类号： H01L21/30 , H01L23/04
CPC分类号： H01L21/304 , H01L25/0657 , H01L25/50 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L2924/01078 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor chip having a thickness of 130 micrometers or less includes a mechanically ground bottom surface corresponding to a central circuit area, and a polished bottom surface corresponding to a peripheral scribe area. The mechanically ground bottom surface prevents heavy metals attached onto the bottom surface of the wafer from diffusing toward the source/drain regions of the semiconductor substrate and thereby from degrading the transistor characteristics
摘要翻译：具有130微米或更小的厚度的半导体芯片包括对应于中心电路区域的机械接地底表面和对应于外围划线区域的抛光底面。机械接地底表面防止附着在晶片底表面上的重金属向半导体衬底的源极/漏极区扩散，从而降低晶体管特性

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