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51. 发明申请

US20070118675A1 DATA TRANSFER APPARATUS WITH CONTROL OF BUSES TO OPTIMIZE DATA TRANSFER 有权
标题翻译：数据传输设备控制业务优化数据传输
公开(公告)号：US20070118675A1
公开(公告)日：2007-05-24
申请号：US11623685
申请日：2007-01-16
申请人： Kenichi Kawaguchi
发明人： Kenichi Kawaguchi
IPC分类号： G06F13/14 , G06F13/36
CPC分类号： G06F13/4027 , G06F13/4031 , G06F13/4059 , G06F13/423 , G06F2213/0024
摘要： A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.
摘要翻译：总线桥连接到主总线和辅助总线，并且中继主机和目标之间的数据，每个主站和目标站之间连接到主总线和次总线之间的不同的总线。总线桥包括主总线接口，辅助总线接口，数据FIFO和寄存器块。可由主器件写入的寄存器块包括与主母线和辅助母线相对应的两个寄存器。显示要从目标到主机中继的数据的条目数的中继信息被登记在对应于目标连接到的总线的寄存器中。在读取事务中，主总线接口或辅助总线接口从目标读取数据，直到被注册的中继信息所示量的数据被存储在数据FIFO中。

52. 发明申请

US20070005864A1 Data transfer apparatus and data transfer method 有权
标题翻译：数据传输装置和数据传输方法
公开(公告)号：US20070005864A1
公开(公告)日：2007-01-04
申请号：US11519114
申请日：2006-09-11
申请人： Kenichi Kawaguchi
发明人： Kenichi Kawaguchi
IPC分类号： G06F13/14
CPC分类号： G06F13/362
摘要： A data transfer apparatus for transferring data between a system bus and a local bus at a high speed is provided. A bus bridge 101 is connected between a system bus 132 and a local bus 137. Data transferred between a CPU 133, an I/O device 136 and a main memory 135 on the system bus 132 are retained in an associative memory 106 via an associative memory control unit 105. When an access to this data from an I/O device 138 on the local bus 137 is generated, the data are transferred from the associative memory 106 to the I/O device 138. Thus, when a data transfer request from the I/O device 138 to the main memory 135 is generated, no bus cycle is generated on the system bus 132 as long as this data are retained in the associative memory 106. Consequently, the data can be transferred at a high speed.
摘要翻译：提供了一种用于在系统总线和本地总线之间高速传输数据的数据传送装置。总线桥101连接在系统总线132和本地总线137之间。在CPU 133，I / O设备136和系统总线132上的主存储器135之间传送的数据经由关联式存储器106保留在关联存储器106中存储器控制单元105。当生成来自本地总线137上的I / O设备138的该数据的访问时，数据从关联存储器106传送到I / O设备138。因此，当产生从I / O设备138到主存储器135的数据传输请求时，只要该数据被保留在关联存储器106中，就不会在系统总线132上产生总线周期。因此，可以高速地传送数据。

53. 发明授权

US07130952B2 Data transmit method and data transmit apparatus 有权
标题翻译：数据发送方式和数据发送装置
公开(公告)号：US07130952B2
公开(公告)日：2006-10-31
申请号：US10765993
申请日：2004-01-29
申请人： Hidenori Nanki , Kenichi Kawaguchi
发明人： Hidenori Nanki , Kenichi Kawaguchi
IPC分类号： G06F13/40 , G06F13/12 , G06F13/16
CPC分类号： H03M7/04 , G11B20/10527 , G11B2020/10546 , G11B2020/10759
摘要： In an arrangement in which a CPU transmits data such as audio data through a 32-bit data bus, a format conversion device and a format conversion program are a are newly prepared. Further, input data having a first bit-width (32 bit width) is converted to output data having a second bit-width (24 bit width) in accordance with a predetermined system so that the efficiency of use of the bus at the time of transmitting data is improved; thus, it becomes possible to reduce a data memory area required for multi-media processes.
摘要翻译：在CPU通过32位数据总线发送诸如音频数据的数据的布置中，新准备了格式转换装置和格式转换程序。此外，具有第一位宽（32位宽）的输入数据根据预定系统被转换为具有第二位宽（24位宽）的输出数据，从而使得总线的使用效率在传输数据得到改善; 因此，可以减少多媒体处理所需的数据存储区域。

54. 发明授权

US06976245B2 PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE UNRELATED TO THE UNITS IN WHICH INSTRUCTIONS ARE READ, AND A COMPILER, AN OPTIMIZATION APPARATUS, AN ASSEMBLER, A LINKER, A DEBUGGER AND A DISASSEMBLER FOR SUCH PROCESSOR 有权
标题翻译：执行单元中指令的处理程序，与指令读取的单元相关，以及编译器，优化设备，汇编器，链接器，调试器和此类处理器的分解器
公开(公告)号：US06976245B2
公开(公告)日：2005-12-13
申请号：US10012725
申请日：2001-10-22
申请人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
发明人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G09F9/44
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30152 , G06F9/30167 , G06F9/321 , G06F9/322 , G06F9/324 , G06F9/3822 , G06F9/3853
摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.
摘要翻译：当分支指令由指令解码器409a〜409c解码时，分支指令中包含的PC相对值的高29位被发送到上PC计算器411，低3位被发送到下PC计算器 405。下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

55. 发明申请

US20050027949A1 Memory device control system 失效
标题翻译：存储设备控制系统
公开(公告)号：US20050027949A1
公开(公告)日：2005-02-03
申请号：US10751659
申请日：2004-01-06
申请人： Kouichi Iwamori , Ikuko Fujinawa , Yoshimasa Obayashi , Kenichi Kawaguchi
发明人： Kouichi Iwamori , Ikuko Fujinawa , Yoshimasa Obayashi , Kenichi Kawaguchi
IPC分类号： G06F3/06 , G06F9/46 , G06F12/00
CPC分类号： G06F9/5027 , G06F2209/5017
摘要： Even if a plurality of tasks that access a plurality of data areas each having the different control method are operated in parallel and the access requests are generated almost simultaneously, the simultaneous accesses to the memory device can be prevented and also a plurality of tasks can be operated in parallel while maintaining a real-time characteristic since the access request contained in the tasks are divided into partial request units by the access-request mediating portion to switch the access requests.
摘要翻译：即使并行地进行访问具有不同控制方式的多个数据区域的多个任务，并且几乎同时生成访问请求，也可以防止对存储装置的同时访问，并且还可以进行多个任务并行操作，同时保持实时特性，因为包含在任务中的访问请求被访问请求中介部分分成部分请求单元以切换访问请求。

56. 发明授权

US06590168B2 Vehicle load measuring apparatus 失效
标题翻译：车载测量装置
公开(公告)号：US06590168B2
公开(公告)日：2003-07-08
申请号：US09778868
申请日：2001-02-08
申请人： Kenichi Kawaguchi , Masayuki Terada , Kouhei Hasimoto , Yoji Nakazaki
发明人： Kenichi Kawaguchi , Masayuki Terada , Kouhei Hasimoto , Yoji Nakazaki
IPC分类号： G01G1908
CPC分类号： G01G19/08
摘要： An amount of distortion of an axle (2) caused by a load that is applied on a vehicle and transmitted to the axle (2) through a transmission member (3) is measured and then a value of the load based on the measured amount of the distortion is measured. A load concentration unit (5) is provided between the transmission member (3) and the axle (2) and receives the load concentrically.
摘要翻译：测量由施加在车辆上并通过传动部件（3）传递到轴（2）的负载引起的轴（2）的变形量，然后测量负载的值测量失真。负载集中单元（5）设置在传动部件（3）和轴（2）之间并同心地接收负载。

57. 发明授权

US06360312B1 Processor for making more efficient use of idling components and program conversion apparatus for the same 有权
标题翻译：用于更高效地使用怠速组件和程序转换装置的处理器
公开(公告)号：US06360312B1
公开(公告)日：2002-03-19
申请号：US09280363
申请日：1999-03-29
申请人： Kenichi Kawaguchi
发明人： Kenichi Kawaguchi
IPC分类号： G06F1500
CPC分类号： G06F9/3001 , G06F9/3017 , G06F9/3822 , G06F9/3853 , G06F9/3885
摘要： A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by a first functional unit that executes instructions stored in the first instruction slot, and a second functional unit that executes instructions stored in the second instruction slot. An instruction stored in the second instruction slot is executed in parallel by a third functional unit that executes instructions stored in the second instruction slot.
摘要翻译：具有多个指令槽的处理器，每个指令槽存储要并行执行的指令。多个指令时隙中的一个是第一指令时隙，另一个是第二指令时隙。存储在第一指令槽中的特殊指令由执行存储在第一指令槽中的指令的第一功能单元和执行存储在第二指令槽中的指令的第二功能单元执行。存储在第二指令槽中的指令由执行存储在第二指令槽中的指令的第三功能单元并行执行。

58. 发明申请

US20130126941A1 SEMICONDUCTOR OPTICAL DEVICE 有权
标题翻译：半导体光学器件
公开(公告)号：US20130126941A1
公开(公告)日：2013-05-23
申请号：US13613177
申请日：2012-09-13
申请人： Lei Zhu , Shigeaki Sekiguchi , Shinsuke Tanaka , Kenichi Kawaguchi
发明人： Lei Zhu , Shigeaki Sekiguchi , Shinsuke Tanaka , Kenichi Kawaguchi
IPC分类号： H01L31/105
CPC分类号： G02B6/122 , G02B6/29352 , G02B2006/121 , G02F1/025 , H01L31/105
摘要： A semiconductor optical device includes a first clad layer, a second clad layer and an optical waveguide layer sandwiched between the first clad layer and the second clad layer, wherein the optical waveguide layer includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer and extending in one direction, and a third semiconductor layer covering a top surface of the second semiconductor layer, and wherein the first semiconductor layer includes an n-type region disposed on one side of the second semiconductor layer, a p-type region disposed on the other side of the second semiconductor layer, and an i-type region disposed between the n-type region and the p-type region, and wherein the second semiconductor layer has a band gap narrower than band gaps of the first semiconductor layer and the third semiconductor layer.
摘要翻译：半导体光学器件包括第一覆盖层，第二覆盖层和夹在第一覆盖层和第二覆盖层之间的光波导层，其中，光波导层包括第一半导体层，第二半导体层，设置在第一覆盖层半导体层并且沿一个方向延伸，以及覆盖第二半导体层的顶表面的第三半导体层，并且其中第一半导体层包括设置在第二半导体层一侧的n型区域，p型区域设置在第二半导体层的另一侧，以及设置在n型区域和p型区域之间的i型区域，并且其中第二半导体层具有比第一半导体层的带隙窄的带隙和第三半导体层。

59. 发明申请

US20120228108A1 Operation Switch 有权
标题翻译：操作开关
公开(公告)号：US20120228108A1
公开(公告)日：2012-09-13
申请号：US13510081
申请日：2010-11-08
申请人： Kenichi Kawaguchi , Masazumi Taniguchi , Atsushi Matsumoto , Masashi Fujimoto , Yasuo Onishi
发明人： Kenichi Kawaguchi , Masazumi Taniguchi , Atsushi Matsumoto , Masashi Fujimoto , Yasuo Onishi
IPC分类号： H01H1/26
CPC分类号： H01H13/20 , H01H1/26 , H01H3/022 , H01H5/18 , H01H13/02 , H01H13/36 , H01H13/62
摘要： A push button switch 1 is so constructed as to disengage the movable contacts 55b, 56b from the fixed contacts 55a, 56a through operation of the push button 2 held in the switch case 3. A first leaf spring 550 is provided in the switch case 3 to act as an opening-biasing means to bias the movable contacts 55b, 56b away from the fixed contacts 55a, 56a. The movable contact 55b is disposed at an end of the first leaf spring 550 and adapted to engage with and disengage from the fixed contact 55a. The first leaf spring 550 is adapted to be at a position where the movable contact 55b is open relative to and disengaged from the fixed contact 55a at zero displacement of the first leaf spring 550.
摘要翻译：按钮开关1被构造成通过操作保持在开关壳体3中的按钮2而将可动触点55b，56b与固定触点55a，56a分离。第一板簧550设置在开关壳体3中以用作将可动触点55b，56b偏离固定触点55a，56a的打开偏压装置。可移动触点55b设置在第一板簧550的端部并且适于与固定触点55a接合和脱开。第一片簧550适于在第一片簧550的零位移处于可动触头55b相对于固定触点55a并相对于其脱开的位置。

60. 发明授权

US08171922B2 Blow-by gas recirculation system for internal combustion engine 有权
标题翻译：内燃机吹气再循环系统
公开(公告)号：US08171922B2
公开(公告)日：2012-05-08
申请号：US12395899
申请日：2009-03-02
申请人： Fusatoshi Tanaka , Katsunori Kuremiya , Kenichi Kawaguchi
发明人： Fusatoshi Tanaka , Katsunori Kuremiya , Kenichi Kawaguchi
IPC分类号： F01M13/00
CPC分类号： F02M25/06 , F01M13/0011 , F01M13/022 , F01M13/04 , F01M2013/0461 , Y02T10/121
摘要： The invention relates to a blow-by gas recirculation system for an internal combustion engine. An oil separation cover 10 has a surge-tank mounting portion 400 integrally formed therewith in a columnar shape having a cam-shaped cross-section and a height approximately equal to that of an oil separation space OS. The surge-tank mounting portion 400 has a flat upper surface serving as a mounting seat surface 401 capable of coming into surface contact with an attaching seat surface 7a of a surge tank 7. A first opening 403 of a gas passage from a chamber 300 is opened in a vicinity of an opening of a support through-hole 402 on the mounting seat surface 401. Through an operation of joining the seat surface 7a of the surge tank 7 to the mounting seat surface 401 of the surge-tank mounting portion 400 while communicating the first opening 403 with a second opening 7b opened on the attaching seat surface 7a of the surge tank 7, a third gas passage 15 for supplying blow-by gas to an inside of the surge tank 7 is formed in such a manner as to penetrate through the oil separation cover 10 and the surge tank 7.
摘要翻译：本发明涉及一种用于内燃机的窜气再循环系统。油分离盖10具有与其一体形成为具有凸轮形横截面和大致等于油分离空间OS的高度的高度的柱状的缓冲罐安装部分400。缓冲罐安装部分400具有平坦的上表面，用作能够与缓冲罐7的安装座表面7a进行表面接触的安装座表面401.来自腔室300的气体通道的第一开口403是在安装座表面401上的支撑通孔402的开口附近开口。通过将缓冲罐7的座面7a连接到缓冲罐安装部400的安装座表面401的操作，同时将第一开口403与在缓冲罐7的安装座表面7a上开口的第二开口7b连通，用于向缓冲罐7内部供给窜气的第三气体通道15形成为：穿过油分离盖10和缓冲罐7。

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