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51. 发明授权

US5694364A Semiconductor integrated circuit device having a test mode for reliability evaluation 失效
标题翻译：具有用于可靠性评估的测试模式的半导体集成电路器件
公开(公告)号：US5694364A
公开(公告)日：1997-12-02
申请号：US779186
申请日：1997-01-06
申请人： Fukashi Morishita , Masaki Tsukude , Kazutami Arimoto
发明人： Fukashi Morishita , Masaki Tsukude , Kazutami Arimoto
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C29/00 , G11C29/06 , H01L21/822 , H01L27/04 , G11C7/00
CPC分类号： G11C5/147
摘要： In the normal mode, a first voltage-down converter down-converts an external power supply voltage to provide a large, first internal power supply voltage to the peripheral circuitry via a first internal power supply voltage supplying line, and a second voltage-down converter down-converts the external power supply voltage to provide a smaller, second internal power supply voltage to a memory cell array via a second internal power supply voltage supplying line. This allows fast operation and reduction in power consumption. In conducting a burn-in test, an external power supply voltage supplying line is connected to the first and second internal power supply voltage supplying lines. Thus, the first and second internal power supply voltage supplying lines directly receive the external power supply voltage. This allows an effective burn-in test. In a burn-in test, the first and second voltage-down converters are inactivated.
摘要翻译：在正常模式中，第一降压转换器对外部电源电压进行下变频，以经由第一内部电源电压供应线向外围电路提供大的第一内部电源电压，以及第二降压转换器降低外部电源电压，以经由第二内部电源电压供给线向存储单元阵列提供较小的第二内部电源电压。这允许快速操作和降低功耗。在进行老化试验时，外部电源电压供给线与第一和第二内部电源电压供给线连接。因此，第一和第二内部电源电压供给线直接接收外部电源电压。这允许有效的老化测试。在老化测试中，第一和第二降压转换器失效。

52. 发明授权

US5659517A Semiconductor memory device with an improved hierarchical power supply line configuration 失效
标题翻译：具有改进的分层电源线配置的半导体存储器件
公开(公告)号：US5659517A
公开(公告)日：1997-08-19
申请号：US486751
申请日：1995-06-06
申请人： Kazutami Arimoto , Masaki Tsukude
发明人： Kazutami Arimoto , Masaki Tsukude
IPC分类号： G11C11/408 , G11C5/14 , G11C11/407 , G11C11/4074 , G11C11/413 , H01L21/822 , H01L27/04 , H01L27/06 , H03K19/00 , G11C7/00
CPC分类号： G11C11/4074 , G11C5/14 , G11C5/147
摘要： In a semiconductor integrated circuit device, a voltage setting circuit for setting a voltage level on the sub power source voltage line according to a reference voltage from a reference voltage generating circuit, is provided between a main power source voltage line and a sub power source voltage line. While a current consumption at the standby cycle is reduced, increase of the access delay is prevented. The voltage setting circuit includes a differential amplifier for differentially amplifying a voltage on the sub power source line and the reference voltages and a transistor responsive to an output of the differential amplifier for causing a current flow between the main and sub power source lines, or alternatively a diode-connected insulated gate type transistor receiving the reference voltage at a back gate thereof.
摘要翻译：在半导体集成电路装置中，在主电源电压线和副电源电压之间设置用于根据来自基准电压发生电路的基准电压设定副电源电压线上的电压电平的电压设定电路线。虽然在备用周期的电流消耗减少，但是阻止了访问延迟的增加。电压设定电路包括用于差分放大副电源线上的电压和参考电压的差分放大器，以及响应于差分放大器的输出以在主电源线和副电源线之间引起电流的晶体管，或者二极管连接的绝缘栅型晶体管，在其后栅极接收参考电压。

53. 发明授权

US5757175A Constant current generating circuit 失效
标题翻译：恒流发电电路
公开(公告)号：US5757175A
公开(公告)日：1998-05-26
申请号：US782036
申请日：1997-01-13
申请人： Fukashi Morishita , Masaki Tsukude , Tsukasa Ooishi , Kyoji Yamasaki
发明人： Fukashi Morishita , Masaki Tsukude , Tsukasa Ooishi , Kyoji Yamasaki
IPC分类号： G05F3/26 , G05F3/24 , G11C11/407 , H03F3/343 , G05F3/16
CPC分类号： G05F3/242
摘要： A current source is provided between a first p channel MOS transistor and a ground node, and a current/voltage converting element is provided isolatedly from the current source between the ground node and a second p channel MOS transistor having a conductance coefficient sufficiently larger than that of the first MOS transistor. The second MOS transistor is connected through a resistive element to an external power supply node. A voltage produced by the current/voltage converting element is converted into current by a voltage/current converting portion. Thus, constant current free from both vibration and a deadlock phenomenon and with small external power supply voltage dependency is supplied.
摘要翻译：在第一p沟道MOS晶体管和接地节点之间提供电流源，并且电流/电压转换元件与接地节点和具有足够大的电导系数的第二p沟道MOS晶体管之间的电流源隔离地提供。的第一MOS晶体管。第二MOS晶体管通过电阻元件连接到外部电源节点。由电流/电压转换元件产生的电压由电压/电流转换部分转换成电流。因此，提供不受振动和死锁现象以及小外部电源电压依赖性的恒定电流。

54. 发明授权

US06707735B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06707735B2
公开(公告)日：2004-03-16
申请号：US10120445
申请日：2002-04-12
申请人： Ryu Makabe , Masaki Tsukude , Hirotoshi Sato
发明人： Ryu Makabe , Masaki Tsukude , Hirotoshi Sato
IPC分类号： G11C700
CPC分类号： G11C29/46
摘要： When address signal bits and/or data bits in a predetermined pattern are accessed a predetermined number of times successively, a test mode can be set. By using address signal bits and/or data bits as a test command for designating a test content, a test content is specified. A semiconductor memory device with an interface compatible with an interface of a normal static random access memory is provided.
摘要翻译：当预定模式的地址信号位和/或数据位连续访问预定次数时，可以设置测试模式。通过使用地址信号位和/或数据位作为用于指定测试内容的测试命令，指定测试内容。提供具有与普通静态随机存取存储器的接口兼容的接口的半导体存储器件。

55. 发明授权

US06590823B2 Refresh-circuit-containing semiconductor memory device 失效
公开(公告)号：US06590823B2
公开(公告)日：2003-07-08
申请号：US09988172
申请日：2001-11-19
申请人： Masaki Tsukude
发明人： Masaki Tsukude
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A refresh circuit performs directive operation for the execution of refresh operation in response to a cycle signal cyclically output from a timer circuit provided in a command-signal activating circuit. To execute testing, a stop signal generated in response to an external signal is activated, the activated stop signal is input to an AND gate, and the cycle signal is thereby invalidated. This causes the refresh operation to terminate, thereby enabling this semiconductor memory device to refresh characteristic testing to be performed.

56. 发明授权

US06556485B2 Output buffer capable of adjusting current drivability and semiconductor integrated circuit device having the same 失效
公开(公告)号：US06556485B2
公开(公告)日：2003-04-29
申请号：US09972242
申请日：2001-10-09
申请人： Tadayuki Shimizu , Hirotoshi Sato , Masaki Tsukude
发明人： Tadayuki Shimizu , Hirotoshi Sato , Masaki Tsukude
IPC分类号： G11C700
CPC分类号： G11C7/1051
摘要： An output buffer includes first current driving units connected in parallel between a power-supply voltage and an output node; second current driving units connected in parallel between a ground voltage and an output node; a plurality of operation selection circuits setting the respective first and second current driving units to be in either activated or inactivated state in a non-volatile manner; first signal transmission circuits arranged respectively corresponding to the first current driving circuits and each transmitting the level of output data with a similar first propagation time period; and second signal transmission circuits arranged respectively corresponding to the second current driving units and each transmitting the level of the output data with a similar second propagation time period.

57. 发明授权

US6038183A Semiconductor memory device having burn-in mode operation stably accelerated 失效
标题翻译：具有老化模式操作的半导体存储器件稳定地加速
公开(公告)号：US6038183A
公开(公告)日：2000-03-14
申请号：US288019
申请日：1999-04-08
申请人： Masaki Tsukude
发明人： Masaki Tsukude
IPC分类号： G01R31/28 , G01R31/30 , G11C5/00 , G11C11/401 , G11C11/407 , G11C29/06 , G11C7/00
CPC分类号： G11C29/06 , G11C29/12005 , G11C29/26 , G11C29/34 , G11C29/50 , G11C5/00 , G11C11/401 , G11C2029/1202 , G11C2029/2602
摘要： Current is reduced in driving a word line in stress acceleration testing such as burn-in, and the time required for the stress acceleration testing is reduced. For an address signal applied from an address buffer, a predetermined internal address signal bit is degenerated and a remaining address signal bit is rendered valid in response to an activation of a stress acceleration mode designation signal to simultaneously drive a desired number of word lines of all word lines to selected state. Any number of word lines can be simultaneously selected and hence current flowing in driving word lines can be reduced in the stress acceleration mode. In the stress acceleration mode of operation, bit line voltage and cell plate voltage are changed, and a current required for driving a plurality of word lines into a selected state is limited.
摘要翻译：压力加速度测试（如老化）中的字线驱动电流减少，应力加速测试所需的时间减少。对于从地址缓冲器施加的地址信号，预定的内部地址信号位退化，并且剩余地址信号位响应于应力加速模式指定信号的激活而变为有效，以同时驱动所需数量的所有字线字线到选定状态。可以同时选择任何数量的字线，因此在应力加速模式中可以减少在驱动字线中流动的电流。在应力加速操作模式中，位线电压和单元板电压发生变化，并且将多条字线驱动到选定状态所需的电流受到限制。

58. 发明授权

US6011428A Voltage supply circuit and semiconductor device including such circuit 失效
标题翻译：电源电路和包括这种电路的半导体器件
公开(公告)号：US6011428A
公开(公告)日：2000-01-04
申请号：US135650
申请日：1993-10-14
申请人： Masaki Tsukude , Masanori Hayashikoshi
发明人： Masaki Tsukude , Masanori Hayashikoshi
IPC分类号： G05F1/56 , G05F3/24 , G11C5/14 , G11C11/401 , G11C11/407 , H03K5/003 , G05F1/10
CPC分类号： G05F3/245 , G05F3/24 , G11C5/147 , Y10S323/907
摘要： The level shifter circuit of an internal down converter includes a P channel MOS transistor constituting a resistance component, and a resistor constituting a resistance component. The temperature coefficient of resistance component is set larger than the temperature coefficient of resistance component so that the output voltage of level shifter circuit has a negative temperature characteristic. If a reference voltage generated by reference voltage generation circuit decreases when operating at a high temperature, the output voltage of level shifter circuit decreases as well. Thus, change in an internal voltage due to change in the operation temperature can be compensated.
摘要翻译：内部下变频器的电平移位电路包括构成电阻分量的P沟道MOS晶体管和构成电阻分量的电阻。电阻分量的温度系数设定为大于电阻分量的温度系数，使得电平移位器电路的输出电压具有负温度特性。如果在高温工作时由参考电压产生电路产生的参考电压降低，则电平转换器电路的输出电压也会降低。因此，可以补偿由于操作温度的变化引起的内部电压的变化。

59. 发明授权

US5987619A Input signal phase compensation circuit capable of reliably obtaining external data 失效
标题翻译：能够可靠地获得外部数据的输入信号相位补偿电路
公开(公告)号：US5987619A
公开(公告)日：1999-11-16
申请号：US947372
申请日：1997-10-08
申请人： Takeshi Hamamoto , Masaki Tsukude
发明人： Takeshi Hamamoto , Masaki Tsukude
IPC分类号： G11C11/407 , G06F1/10 , G11C11/409 , G06F1/04
CPC分类号： G06F1/10
摘要： An input signal phase compensation circuit having a monitor mode and a normal operation mode includes a mode switching circuit, a logic gate receiving an internal data signal, a delay circuit connected to the logic gate, and a phase comparator comparing, in the monitor mode, phases of a signal output from the delay circuit and a clock signal, and determining time for delaying an internal clock signal in a variable delay circuit so as to match phases of the both signals. In the normal operation mode, the time is fixed, and data is obtained at phase compensated timing.
摘要翻译：具有监视模式和正常操作模式的输入信号相位补偿电路包括模式切换电路，接收内部数据信号的逻辑门，连接到逻辑门的延迟电路，以及在监视器模式下，从延迟电路输出的信号的相位和时钟信号，以及确定用于延迟可变延迟电路中的内部时钟信号的时间，以便匹配两个信号的相位。在正常工作模式下，时间是固定的，并且在相位补偿定时获得数据。

60. 发明授权

US5982698A Multi-bank system semiconductor memory device capable of operating at high speed 失效
标题翻译：能够高速运转的多存储体系半导体存储器件
公开(公告)号：US5982698A
公开(公告)日：1999-11-09
申请号：US215927
申请日：1998-12-18
申请人： Masaki Tsukude
发明人： Masaki Tsukude
IPC分类号： G11C11/401 , G11C7/06 , G11C8/00 , G11C8/12 , G11C11/407 , G11C11/409
CPC分类号： G11C7/06 , G11C8/12
摘要： A semiconductor integrated circuit device of the present invention includes a plurality of banks and a plurality of sense amplifier bands. A switch circuit included in each sense amplifier band receives a signal on a transmission line and outputs a signal read from the bank to a global data input/output line arranged in the column direction. A column bank control circuit for outputting a column bank control signal is arranged on the column decoder side. The column bank control signal is supplied to the transmission line through a column bank control signal line arranged in the column direction. The switch circuit operates in accordance with the column bank control signal. By such a configuration, a column-related operation can be matched easily.
摘要翻译：本发明的半导体集成电路器件包括多个堤和多个读出放大器带。包括在每个读出放大器带中的开关电路接收传输线上的信号，并将从存储体读出的信号输出到沿列方向布置的全局数据输入/输出线。用于输出列组控制信号的列组控制电路被布置在列解码器侧。列列控制信号通过沿列方向布置的列组控制信号线提供给传输线。开关电路根据列组控制信号进行工作。通过这样的配置，可以容易地匹配列相关操作。

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