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    • 53. 发明申请
    • SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit thereof
    • SET / RESET锁存电路,施密特触发电路和基于MOBILE的D型触发器电路及其分频器电路
    • US20070069810A1
    • 2007-03-29
    • US11418207
    • 2006-05-05
    • Kyoung-Hoon YangTae-Ho Kim
    • Kyoung-Hoon YangTae-Ho Kim
    • H03B7/06H03K17/58H03K19/10H03K19/02G06F17/50
    • H03K3/315H03K3/2885H03K3/2897H03K5/00006H03K17/58
    • The present invention relates to SET/RESET latch circuit, Schmitt trigger circuit, and MOBILE based D-type flip flop circuit and frequency divider circuit using the SET/RESET latch circuit and Schmitt trigger circuit. Herein, SET/RESET latch circuit is especially configured with CML-type transistors and negative differential resistance diodes. The SET/RESET latch circuit can be applied for very high speed digital circuits A SET/RESET latch circuit, characterized by including a transistor 1 and 2 in which each emitter of said transistors is commonly connected to a current source, and a negative differential resistance diode 1 and 2 which are respectively connected to each collector of said transistor 1 and 2; and additionally performing to be the relationship of IP
    • 本发明涉及使用SET / RESET锁存电路和施密特触发电路的SET / RESET锁存电路,施密特触发电路和基于MOBILE的D型触发器电路和分频器电路。 这里,SET / RESET锁存电路特别配置有CML型晶体管和负差分电阻二极管。 SET / RESET锁存电路可以应用于非常高速的数字电路A SET / RESET锁存电路,其特征在于包括晶体管1和2,其中所述晶体管的每个发射极共同连接到电流源,负差分电阻 二极管1和2分别连接到所述晶体管1和2的每个集电极; 并且另外执行以下的关系:其中,I P :所述负差分电阻二极管1和2的峰值电流为:与所述晶体管1和2的发射极的公共节点串联连接的电流源的电流; 从而在分别在所述晶体管1和2的基端口上提供归零模式SET和RESET电压的情况下提供单个和差分非归零模式输出。