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51. 发明授权

US06900138B1 Oxygen plasma treatment for nitride surface to reduce photo footing 有权
标题翻译：氧等离子体处理氮化物表面以减少照片基础
公开(公告)号：US06900138B1
公开(公告)日：2005-05-31
申请号：US09259762
申请日：1999-03-01
申请人： Zhiping Yin , Mark Fischer
发明人： Zhiping Yin , Mark Fischer
IPC分类号： H01L21/027 , H01L21/318 , H01L21/302
CPC分类号： H01L21/3185 , H01L21/0274
摘要： The present invention includes a method for preventing distortion in semiconductor fabrication. The method comprises providing a substrate comprising a film comprising silicon nitride. The substrate is treated in a vacuum of about 3.0-6.5 Torr in an atmosphere comprising oxygen plasma wherein the oxygen plasma flow rate is at least about 300 sccm oxygen. A resist is applied to the treated substrate and the resist is patterned over the treated substrate.
摘要翻译：本发明包括一种用于防止半导体制造中的变形的方法。该方法包括提供包含含氮化硅的膜的衬底。在包含氧等离子体的气氛中，在约3.0-6.5乇的真空中处理衬底，其中氧等离子体流速为至少约300sccm的氧气。将抗蚀剂施加到经处理的基底上，并且将抗蚀剂图案化在经处理的基底上。

52. 发明授权

US06440850B1 Structure for an electrical contact to a thin film in a semiconductor structure and method for making the same 有权
标题翻译：用于与半导体结构中的薄膜的电接触的结构及其制造方法
公开(公告)号：US06440850B1
公开(公告)日：2002-08-27
申请号：US09385586
申请日：1999-08-27
申请人： Kunal R. Parekh , Mark Fischer , Charles H. Dennison
发明人： Kunal R. Parekh , Mark Fischer , Charles H. Dennison
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A network of electrically conductive plate contacts is provided within the structure of a DRAM chip to enable storage of non-zero voltage levels in each charge storage region. An improved cell or top plate contact provides low contact resistance and improved structural integrity making the contact less prone to removal during subsequent processing steps. A top plate conformally lines a container patterned down into a subregion. A metal contact structure comprises a waist section, a contact leg, and an anchor leg. The contact leg makes contact to the top plate within the container interior. The waist section joins the top of the contact leg to the top of the anchor leg and extends over the edge of the top plate. The anchor leg extends downward through the subregion adjacent to but spaced from the container to anchor the structure in place and provide structural integrity. Accordingly, the present invention provides an improved structure for contact to a conductive thin film, having low contact resistance and an improved structural integrity.
摘要翻译：在DRAM芯片的结构内提供导电板触点的网络，以便能够在每个电荷存储区域中存储非零电压电平。改进的电池或顶板接触提供低接触电阻和改进的结构完整性，使得接触在随后的加工步骤期间更不易于去除。顶板共形地将图案化的容器图案化成一个子区域。金属接触结构包括腰部，接触腿和锚腿。接触腿与容器内部的顶板接触。腰部将接触腿的顶部连接到锚腿的顶部并且在顶板的边缘上延伸。锚腿向下延伸穿过与容器相邻但与容器间隔开的子区域，以将结构锚定在适当位置并提供结构完整性。因此，本发明提供了一种与导电薄膜接触的改进的结构，具有低的接触电阻和改进的结构完整性。

53. 发明授权

US06376358B1 Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications 有权
公开(公告)号：US06376358B1
公开(公告)日：2002-04-23
申请号：US09809666
申请日：2001-03-15
申请人： Mark Fischer , Jigish D. Trivedi , Charles H. Dennison , Todd R. Abbott , Raymond A. Turi
发明人： Mark Fischer , Jigish D. Trivedi , Charles H. Dennison , Todd R. Abbott , Raymond A. Turi
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , G11C2207/104 , H01L21/76889 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10888
摘要： A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for the operation of the DRAM and SRAM or logic. Also disclosed are systems-on-chips MIM/MIS capacitive devices produced by the inventive process.

54. 发明授权

US6083803A Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances 失效
公开(公告)号：US6083803A
公开(公告)日：2000-07-04
申请号：US32254
申请日：1998-02-27
申请人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
发明人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
IPC分类号： H01L21/302 , G03F7/075 , G03F7/16 , H01L21/3065 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10888 , G03F7/0757 , G03F7/167 , H01L21/76838 , H01L27/10852
摘要： Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug. In another aspect, conductive plug material is unevenly doped with dopant, and conductive plug material containing greater concentrations of dopant is etched at a greater rate than plug material containing lower concentrations of dopant.

55. 发明授权

US5962885A Method of forming a capacitor and a capacitor construction 失效
标题翻译：电容器结构
公开(公告)号：US5962885A
公开(公告)日：1999-10-05
申请号：US935966
申请日：1997-09-23
申请人： Mark Fischer , Mark Jost , Kunal Parekh
发明人： Mark Fischer , Mark Jost , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L28/40 , Y10S148/02
摘要： The invention encompasses capacitor constructions. In one aspect, the invention includes a stacked capacitor construction comprising: a) a substrate; b) an electrically conductive runner provided on the substrate, the runner having an outer conductive surface; c) a node on the substrate adjacent the electrically conductive runner; d) an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node adjacent the conductive runner, the pillar having an outer surface; e) an electrically conductive storage node container layer in electrical connection with the pillar; f) a capacitor dielectric layer over the capacitor storage node layer; and g) an electrically conductive outer capacitor plate over the capacitor dielectric layer; and h) the pillar outer surface being elevationally inward of the runner outer surface.
摘要翻译：本发明包括电容器结构。一方面，本发明包括堆叠式电容器结构，其包括：a）衬底; b）设置在所述基底上的导电流道，所述流道具有外导电表面; c）邻近导电流道的衬底上的节点; d）与所述节点电连接的导电柱，所述柱相对于邻近导电流道的节点向外突出，所述柱具有外表面; e）与所述支柱电连接的导电存储节点容器层; f）电容器存储节点层上的电容器介电层; 和g）电容器介电层上的导电外电容器板; 以及h）所述柱外表面位于所述流道外表面的正上方。

56. 发明授权

US5932491A Reduction of contact size utilizing formation of spacer material over resist pattern 失效
标题翻译：通过在抗蚀剂图案上形成隔离材料来减小接触尺寸
公开(公告)号：US5932491A
公开(公告)日：1999-08-03
申请号：US796399
申请日：1997-02-06
申请人： Phillip G. Wald , Mark Fischer , William A. Stanton
发明人： Phillip G. Wald , Mark Fischer , William A. Stanton
IPC分类号： H01L21/768 , H01L21/00
CPC分类号： H01L21/76831 , H01L21/76807
摘要： A method for forming a sidewall aligned contact structure without a hardmask layer. A semiconductor region is provided having an active area at an upper surface. An insulating layer is formed having an upper surface over the active area. Using a photo-patterned organic mask, a gross contact opening is etched in the insulating layer over the active area. The gross contact opening extends downward from the upper surface and partially through the insulating layer. A conformal layer of material is deposited at low temperature over the patterned mask as well as sidewalls and a bottom surface of the gross contact opening The conformal layer comprises a material that is differentially etchable with respect to the photomask and preferably etches similarly to the insulating layer. A portion of the insulating layer at the base of the gross contact opening is exposed. A contact opining is formed in the exposed portion of the insulating layer using the remaining conformal layer as a mask.
摘要翻译：一种用于形成没有硬掩模层的侧壁对齐接触结构的方法。提供在上表面具有有效面积的半导体区域。在有源区域上形成有上表面的绝缘层。使用光刻图案的有机掩模，在有效区域上的绝缘层中蚀刻总接触开口。总接触开口从上表面向下延伸并且部分地穿过绝缘层。在图案化掩模以及总接触开口的侧壁和底表面上的低温下沉积保形层材料。共形层包括相对于光掩模可差分蚀刻的材料，并且优选类似于绝缘层蚀刻。在总触点开口底部的绝缘层的一部分露出。使用剩余的保形层作为掩模，在绝缘层的暴露部分中形成接触形成。

57. 发明申请

US20160350367A1 Mechanisms For Querying Disparate Data Storage Systems 审中-公开
标题翻译：查询不同数据存储系统的机制
公开(公告)号：US20160350367A1
公开(公告)日：2016-12-01
申请号：US14722330
申请日：2015-05-27
申请人： Mark Fischer , Prakash Khot , Dilip Kumar Vedula , Tong Zhao , Siva Prakash Ragavan , Joseph Paquette
发明人： Mark Fischer , Prakash Khot , Dilip Kumar Vedula , Tong Zhao , Siva Prakash Ragavan , Joseph Paquette
IPC分类号： G06F17/30
摘要： Computer implemented techniques for storage management include receiving a query from an application within an application level, which is received as a standard syntax wrapped query language query, with the standard syntax wrapped query having as a parameter, an identifier to a specific object, determining a platform type on which the received query is executable and translating the standard syntax wrapped query language query into the determined native query language used by the determined data storage platform type.
摘要翻译：用于存储管理的计算机实现的技术包括从作为标准语法包装的查询语言查询接收的应用程序级的应用程序接收查询，标准语法包装查询具有作为参数的标识符，特定对象的标识符，接收到的查询可执行的平台类型，并将标准语法包装查询语言查询转换为由确定的数据存储平台类型使用的确定的本机查询语言。

58. 发明授权

US08674404B2 Additional metal routing in semiconductor devices 有权
标题翻译：半导体器件中的附加金属布线
公开(公告)号：US08674404B2
公开(公告)日：2014-03-18
申请号：US12972232
申请日：2010-12-17
申请人： Terry McDaniel , James Green , Mark Fischer
发明人： Terry McDaniel , James Green , Mark Fischer
IPC分类号： H01L29/66
CPC分类号： H01L27/105 , H01L21/823475 , H01L21/823871 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11531 , H01L29/66545
摘要： Memory devices, such as DRAM memory devices, may include one or more metal layers above a local interconnect of the DRAM memory that make contact to lower gate regions of the memory device. As the size of semiconductor components decreases and circuit densities increase, the density of the metal routing in these upper metal layers becomes increasingly difficult to fabricate. By providing additional metal routing in the lower gate regions that may be coupled to the upper metal layers, the spacing requirements of the upper metal layers may be eased, while maintaining the size of the semiconductor device. In addition, the additional metal routing formed in the gate regions of the memory devices may be disposed parallel to other metal contacts in a strapping configuration, thus reducing a resistance of the metal contacts, such as buried digit lines of a DRAM memory cell.
摘要翻译：诸如DRAM存储器件的存储器件可以包括与存储器件的下部栅极区域接触的DRAM存储器的局部互连上方的一个或多个金属层。随着半导体元件的尺寸减小和电路密度增加，这些上层金属层中的金属布线的密度越来越难于制造。通过在可以耦合到上金属层的下栅极区域中提供额外的金属布线，可以在保持半导体器件的尺寸的同时，缓和上金属层的间隔要求。此外，形成在存储器件的栅极区域中的附加金属布线可以以带状构造平行于其它金属触点设置，从而降低金属触点（例如DRAM存储器单元的掩埋数字线）的电阻。

59. 发明授权

US08409948B2 Methods of forming transistors, and methods of forming memory arrays 有权
标题翻译：形成晶体管的方法，以及形成存储器阵列的方法
公开(公告)号：US08409948B2
公开(公告)日：2013-04-02
申请号：US13485892
申请日：2012-05-31
申请人： Mark Fischer , Sanh D. Tang
发明人： Mark Fischer , Sanh D. Tang
IPC分类号： H01L21/8242 , H01L21/8238
CPC分类号： H01L27/10876 , H01L21/823425 , H01L21/823487 , H01L27/2454 , H01L29/0653 , H01L29/42368 , H01L29/456 , H01L29/66666 , H01L29/7827 , H01L45/06 , H01L45/1233
摘要： Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.
摘要翻译：一些实施例包括形成垂直晶体管的方法。结构可以具有从半导体衬底向上延伸的多个间隔开的翅片。每个鳍片可以具有垂直的晶体管柱，并且每个垂直晶体管柱可以具有底部源极/漏极区域位置，在底部源极/漏极区域位置上方的沟道区域位置，以及顶部源极/漏极区域渠道区域位置。导电栅极材料可以沿着鳍片形成，同时沿着鳍状物的底部在空间内使用氧化物以将导电栅极材料偏移到垂直晶体管柱的底部源极/漏极区域的上方。氧化物可以是在室温下用稀释HF以至少约100埃/分钟的速率蚀刻的氧化物。在一些实施例中，可以在形成导电栅极材料之后去除氧化物。

60. 发明授权

US08326675B2 Method and system for load balancing a sales forecast by selecting a synchronous or asynchronous process based on a type of event affecting the sales forecast 有权
标题翻译：通过基于影响销售预测的事件类型选择同步或异步过程来负载平衡销售预测的方法和系统
公开(公告)号：US08326675B2
公开(公告)日：2012-12-04
申请号：US13353265
申请日：2012-01-18
申请人： Kedar Doshi , Mark Fischer , Evan Chou
发明人： Kedar Doshi , Mark Fischer , Evan Chou
IPC分类号： G06Q10/00 , G06Q30/00
CPC分类号： G06Q10/04 , G06Q10/0639 , G06Q30/0202
摘要： In accordance with embodiments, there are provided mechanisms and methods for selecting a synchronous or asynchronous process to determine a forecast. These mechanisms and methods for such synchronous/asynchronous process selection can enable embodiments to determine forecasts for multiple users (e.g. with hierarchical relationships, etc.) over an arbitrary time interval. The ability of embodiments to provide forecasts that involve such a large amount of data in an effective way can enable forecasting that was otherwise infeasible due to resource limitations.
摘要翻译：根据实施例，提供了用于选择同步或异步过程以确定预测的机制和方法。用于这种同步/异步过程选择的这些机制和方法可使得实施例能够在任意时间间隔上确定多个用户的预测（例如，具有层次关系等）。实施例以有效的方式提供涉及这样大量数据的预测的能力可以使由于资源限制而导致的预测是不可行的。

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