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    • 52. 发明申请
    • APPARATUS FOR MEASURING IQ IMBALANCE
    • 测量智商不平等的方法
    • US20080205502A1
    • 2008-08-28
    • US12027742
    • 2008-02-07
    • Kyeongho LeeJoonbae ParkJeong Woo LeeSeung-Wook LeeEal Wan Lee
    • Kyeongho LeeJoonbae ParkJeong Woo LeeSeung-Wook LeeEal Wan Lee
    • H04B3/46H04B17/00H04Q1/20
    • H04L27/364H04L27/3863
    • The present general inventive concept relates to apparatuses and/or methods for measuring an IQ imbalance. In one embodiment, a detector can measure an error caused by an IQ imbalance using a first IQ signal including a desired signal and a corresponding image signal by the IQ imbalance. The detector can include a derotator to derotate the first IQ signal by a first angular frequency to obtain a second IQ signal and derotate the first IQ signal by a second angular frequency to obtain a third IQ signal, a DC estimator to obtain a fourth IQ signal corresponding to a DC component of the second IQ signal and a fifth IQ signal corresponding to a DC component of the third IQ signal and a controller can determine a gain error or a phase error from the fourth IQ signal and the fifth IQ signal.
    • 本发明总体构思涉及用于测量IQ不平衡的装置和/或方法。 在一个实施例中,检测器可以通过IQ不平衡来使用包括期望信号和对应图像信号的第一IQ信号来测量由IQ不平衡引起的误差。 检测器可以包括解旋器,以将第一IQ信号扭转第一角度频率以获得第二IQ信号并且将第一IQ信号解旋第二角频率以获得第三IQ信号,DC估计器以获得第四IQ信号 对应于第二IQ信号的DC分量和对应于第三IQ信号的DC分量的第五IQ信号,并且控制器可以从第四IQ信号和第五IQ信号确定增益误差或相位误差。
    • 55. 发明授权
    • Circuit for controlling a delay time of input pulse and method of controlling the same
    • 用于控制输入脉冲的延迟时间的电路及其控制方法
    • US07170325B2
    • 2007-01-30
    • US10879835
    • 2004-06-29
    • Jeong Woo Lee
    • Jeong Woo Lee
    • H03K5/04
    • G11C7/222G11C7/1048G11C7/1072G11C2207/002H03K5/05H03K5/135H03K5/156
    • Provided is directed to a circuit of controlling a pulse width and a method of controlling the same, which can remove failure possible to be generated during operations of a DRAM or a DDR in a high frequency by guaranteeing read and write operations of a stabilized data and a precharging time of a local input/output line, in response to identically adjust widths of a pulse synchronized with a clock and a target pulse, by means of comprising: a pulse comparator for comparing a target pulse with a pulse synchronized with a clock; a counter pulse generation circuit for generating a counter pulse according to an output of the comparator; a pulse counter circuit for outputting a plurality of pulse counter signals, sequentially, according to the counter pulse; and a pulse delay circuit for controlling the pulse width synchronized with the clock according to the plurality of pulse counter signals.
    • 提供了一种控制脉冲宽度的电路及其控制方法,其通过保证稳定的数据的读取和写入操作来消除在DRAM或DDR在高频操作期间可能产生的故障,并且 通过包括:用于将目标脉冲与与时钟同步的脉冲进行比较的脉冲比较器,响应于同时调节与时钟和目标脉冲同步的脉冲的宽度,本地输入/输出线的预充电时间; 计数脉冲发生电路,用于根据比较器的输出产生计数脉冲; 脉冲计数器电路,用于根据所述计数脉冲依次输出多个脉冲计数器信号; 以及脉冲延迟电路,用于根据多个脉冲计数器信号控制与时钟同步的脉冲宽度。
    • 56. 发明授权
    • Communication transmitter using offset phase-locked-loop
    • 通信发射机使用偏移锁相环
    • US06963620B2
    • 2005-11-08
    • US10284342
    • 2002-10-31
    • Kang-Yoon LeeEunseok SongJeong Woo LeeJoonbae ParkKyeongho Lee
    • Kang-Yoon LeeEunseok SongJeong Woo LeeJoonbae ParkKyeongho Lee
    • H03C3/09H04L27/04H03D3/24H04L27/12H04L27/20
    • H03C3/0966H03C3/0933
    • A translational-loop transmitter generates RF signals using at most one phase-locked-loop (PLL) circuit. In one embodiment, a single PLL generates two local oscillation signals. The first oscillation signal is mixed with a baseband signal to generate an intermediate frequency signal. The second oscillation signal is input into the translational loop to adjust a voltage-controlled oscillator to the desired carrier frequency. In order to perform this type of modulation, the frequencies of the local oscillation signals are set so that they are harmonically related to one another relative to the carrier frequency. Other embodiments generate only one oscillation signal. Under these conditions, the intermediate frequency signal is generated using the oscillation signal, and a frequency divider in the translational loop is used to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. In still other embodiments, a transmitter signal is generated without using any phase-locked-loop circuits. This is accomplished by generating an intermediate frequency signal using a crystal oscillator, and then using a frequency divider in a feedback loop to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. By minimizing the number of phase-locked-loop circuits in the transmitter, the size, cost, and power requirements of mobile handsets may be significantly reduced.
    • 平移环路发射器使用至多一个锁相环(PLL)电路产生RF信号。 在一个实施例中,单个PLL产生两个本地振荡信号。 第一振荡信号与基带信号混合以产生中频信号。 第二振荡信号被输入到平移回路中,以将压控振荡器调整到期望的载波频率。 为了执行这种类型的调制,本地振荡信号的频率被设置为使得它们相对于载波频率彼此谐波相关。 其他实施例仅产生一个振荡信号。 在这些条件下,使用振荡信号产生中频信号,并且使用平移环路中的分频器产生用于将压控振荡器调节到载波频率的控制信号。 在其他实施例中,产生发射机信号而不使用任何锁相环电路。 这是通过使用晶体振荡器产生中频信号,然后在反馈环路中使用分频器来产生用于将压控振荡器调节到载波频率的控制信号来实现的。 通过最小化发射机中的锁相环电路的数量,移动手机的尺寸,成本和功率要求可能会大大降低。