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    • 51. 发明申请
    • Method for manufacturing semiconductor device
    • 制造半导体器件的方法
    • US20050095838A1
    • 2005-05-05
    • US10880035
    • 2004-06-29
    • Cheol JeongTae Kim
    • Cheol JeongTae Kim
    • H01L27/115H01L21/28H01L21/3205H01L21/44H01L21/4763H01L21/768H01L21/8239H01L27/105
    • H01L27/105H01L21/76838H01L27/1052
    • The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate on which cell strings are formed and in which a plurality of conductive regions are formed; sequentially forming a first interlayer insulation film and a first etch barrier film on the semiconductor substrate; forming a plurality of contact holes by exposing the plurality of conductive regions formed in the semiconductor substrate, wherein an impurity concentration of the conductive regions is reduced due to the process for forming the contact holes; filling a metal material in the contact holes and forming a plurality of contact plugs; sequentially forming a second interlayer insulation film, a second etch barrier film and a third interlayer insulation film over a resulting structure including the contact plugs; forming a plurality of metal line patterns, wherein the metal line patterns pass through the third interlayer insulation film, the second etch barrier film and the second interlayer insulation film and contact to the contact plugs; forming a fourth interlayer insulation film over a resulting structure including the plurality of metal line patterns; forming a plurality of metal line contact holes by patterning the fourth interlayer insulation film; and forming a plurality of metal line contact plugs in the plurality of metal line contact holes by filling a metal material in the metal line contact holes.
    • 本发明公开了一种制造半导体器件的方法,包括以下步骤:提供其上形成有多个导电区域的半导体衬底,其上形成有多个导电区域; 在半导体衬底上依次形成第一层间绝缘膜和第一蚀刻阻挡膜; 通过暴露形成在半导体衬底中的多个导电区域来形成多个接触孔,其中由于形成接触孔的工艺导致导电区域的杂质浓度降低; 在接触孔中填充金属材料并形成多个接触插塞; 在包括接触塞的所得结构上依次形成第二层间绝缘膜,第二蚀刻阻挡膜和第三层间绝缘膜; 形成多个金属线图案,其中所述金属线图案通过所述第三层间绝缘膜,所述第二蚀刻阻挡膜和所述第二层间绝缘膜并与所述接触插塞接触; 在包括所述多个金属线图案的所得结构上形成第四层间绝缘膜; 通过图案化第四层间绝缘膜形成多个金属线接触孔; 以及通过在金属线接触孔中填充金属材料在所述多个金属线接触孔中形成多个金属线接触塞。
    • 54. 发明申请
    • LOW VOLTAGE SENSING SCHEME HAVING REDUCED ACTIVE POWER DOWN STANDBY CURRENT
    • 具有降低有功功率待机电流的低电压感测方案
    • US20110103158A1
    • 2011-05-05
    • US13005453
    • 2011-01-12
    • Tae Kim
    • Tae Kim
    • G11C7/00G11C7/06
    • G11C7/08G11C5/148G11C7/06G11C7/062G11C7/065G11C7/1006G11C7/12G11C7/22G11C11/4091G11C2207/065G11C2207/2227
    • A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
    • 低电压感测方案减少了存储器件中的有功功率下的待机漏电流。 在Psense放大器控制线(例如ACT)和Vcc之间和/或在Nsense放大器控制线(例如RNL *)和Vss(地电位)之间使用钳位装置或二极管。 钳位二极管在正常存储器操作期间不使能,但在有功掉电模式下导通,以减少通过ACT和/或RNL *节点的泄漏电流。 连接到ACT节点的钳位装置可以在掉电模式下降低ACT线路上的电压,而连接到RNL *节点的钳位装置可能会在掉电模式下增加RNL *线路上的电压,以降低读出放大器的漏电流 通过这些节点。 由于管理摘要的规则,本摘要不应用于解释索赔。
    • 56. 发明授权
    • Low voltage sensing scheme having reduced active power down standby current
    • 低电压感测方案具有降低的有功功率的待机电流
    • US07872923B2
    • 2011-01-18
    • US12079765
    • 2008-03-28
    • Tae Kim
    • Tae Kim
    • G11C7/10
    • G11C7/08G11C5/148G11C7/06G11C7/062G11C7/065G11C7/1006G11C7/12G11C7/22G11C11/4091G11C2207/065G11C2207/2227
    • A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may increase because of the use of P and Nsense amplifiers having low threshold voltages (Vth) for low Vcc sensing of data signals. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
    • 低电压感测方案减少了存储器件中的有功功率下的待机漏电流。 在存储器的有功断电状态期间,由于使用具有低阈值电压(Vth)的P和Nsense放大器用于数据信号的低Vcc感测,漏电流可能增加。 在Psense放大器控制线(例如ACT)和Vcc之间和/或在Nsense放大器控制线(例如RNL *)和Vss(地电位)之间使用钳位装置或二极管。 钳位二极管在正常存储器操作期间不使能,但在有功掉电模式下导通,以减少通过ACT和/或RNL *节点的泄漏电流。 连接到ACT节点的钳位装置可以在掉电模式下降低ACT线路上的电压,而连接到RNL *节点的钳位装置可能会在掉电模式下增加RNL *线路上的电压,以降低读出放大器的漏电流 通过这些节点。 由于管理摘要的规则,本摘要不应用于解释索赔。
    • 59. 发明申请
    • Array sense amplifiers, memory devices and systems including same, and methods of operation
    • 阵列读出放大器,包括其的存储器件和系统以及操作方法
    • US20080159035A1
    • 2008-07-03
    • US11646735
    • 2006-12-27
    • Chulmin JungTae Kim
    • Chulmin JungTae Kim
    • G11C7/10G11C7/06
    • G11C7/065G11C11/4091
    • A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on one of the I/O nodes. The first amplifier stage, having a first conductivity-type, amplifies one of the I/O node towards a first voltage. The second amplifier stage, having a second conductivity-type, amplifies the other I/O node towards a second voltage. The sense amplifier also includes a resistance circuit coupled to the second amplifier stage to reduce the gain of the second amplifier stage thereby reducing the rate of amplification of the signal on the corresponding I/O node.
    • 描述了具有减小的增益的放大器级的读出放大器。 读出放大器包括第一输入/输出(“I / O”)节点和第二互补I / O节点。 读出放大器包括两个放大器级,每个用于放大I / O节点之一上的信号。 具有第一导电类型的第一放大器级将第一电压的I / O节点之一放大。 具有第二导电类型的第二放大器级将第二电压放大到另一个I / O节点。 读出放大器还包括耦合到第二放大器级的电阻电路,以减小第二放大器级的增益,从而降低相应I / O节点上的信号的放大率。
    • 60. 发明申请
    • Apparatus and Method For Dualizing an Asynchronous Transfer Mode (Atm) Router in a Cdma2000 System
    • 用于在Cdma2000系统中双向异步传输模式(Atm)路由器的设备和方法
    • US20070291760A1
    • 2007-12-20
    • US10585602
    • 2005-01-14
    • Tae Kim
    • Tae Kim
    • H04L12/28
    • H04L12/5601H04L41/0846H04L45/60H04L49/30H04L49/552H04L2012/5607H04L2012/5618H04L2012/5627H04W24/04H04W88/12
    • The present invention provides an apparatus and method for dualizing an Asynchronous Transfer Mode (ATM) router in a CDMA2000 system. In a conventional wireless communication system, an ATM router in a Base Station Controller (BSC) has two separate dualized main central processing boards, which are also referred to as ADSL Subscriber Physical board Assembly (ASPA) boards. Each of the ASPA boards includes one operation and maintenance processor, which maintains configuration and operation information. One of the conventional dualized ASPA boards transmits its configuration and operation information to the other, or receives the information from the other, in the form of message. This is in order to maintain the consistency between the information of the dualized ASPA boards, as needed. Such message passing, however, is generally time consuming and may possibly create network overload. According to the invention, the dualized ASPA boards communicate the configuration and operation information with each other using a File Transfer Protocol (FTP), rather than by message passing. Accordingly, communicating the information takes relatively less time, which can considerably reduce the whole system loads and decrease the possibility of data inconsistency between the dualized ASPA boards.
    • 本发明提供了一种用于在CDMA2000系统中二次化异步传输模式(ATM)路由器的装置和方法。 在传统的无线通信系统中,基站控制器(BSC)中的ATM路由器具有两个单独的二元化主中央处理板,也被称为ADSL用户物理板组装(ASPA)板。 每个ASPA板包括一个操作和维护处理器,它维护配置和操作信息。 传统的二进制ASPA板之一将其配置和操作信息传输到另一个,或以消息的形式从另一个接收信息。 这是为了根据需要保持二元化ASPA板的信息之间的一致性。 然而,这样的消息传递通常是耗时的,并且可能产生网络过载。 根据本发明,二进制ASPA板使用文件传输协议(FTP)来传送配置和操作信息,而不是通过消息传递。 因此,传达信息所需的时间相对较少,这可以大大减少整个系统负载,并降低二元化ASPA板之间数据不一致的可能性。