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51. 发明申请

US20050052202A1 Limited switch dynamic logic circuit with keeper 失效
标题翻译：限位开关动态逻辑电路与保持器
公开(公告)号：US20050052202A1
公开(公告)日：2005-03-10
申请号：US10655375
申请日：2003-09-04
申请人： Hung Ngo
发明人： Hung Ngo
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： An LSDL circuit has both an output and a complementary output generated by inverting the output with an inverter logic gate. A keeper PFET is added by coupling its drain terminal to the dynamic node. The keeper PFET has its source terminal coupled to the positive power supply voltage and its gate terminal coupled to the complementary output. The output and the dynamic node may both be at a logic one when the output is a logic one from the previous evaluation cycle and the dynamic node is precharged. In this case, the complementary output is a logic zero which turns ON the keeper PFET and reinforces the precharge on the dynamic node. When the output is evaluating to a logic zero, the output will transition quickly to a logic zero. If the output is transitioning from a logic zero to a logic one, then the keeper PFET is OFF and does not affect the dynamic node.
摘要翻译： LSDL电路具有通过用反相器逻辑门反相输出而产生的输出和互补输出。通过将其漏极端子耦合到动态节点来添加保持器PFET。保持器PFET的源极端子耦合到正电源电压，其栅极端子耦合到互补输出。当输出是来自先前评估周期的逻辑1并且动态节点被预充电时，输出和动态节点都可以是逻辑节点。在这种情况下，互补输出为逻辑0，导通保持器PFET并加强动态节点上的预充电。当输出评估为逻辑0时，输出将快速转换为逻辑0。如果输出从逻辑0转换为逻辑0，则保持器PFET为OFF并且不影响动态节点。

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