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51. 发明申请

US20130070549A1 Single-Ended Sense Amplifier with Read-Assist 失效
标题翻译：具有读辅助功能的单端读出放大器
公开(公告)号：US20130070549A1
公开(公告)日：2013-03-21
申请号：US13234218
申请日：2011-09-16
申请人： Amlan Ghosh , Jente B. Kuang
发明人： Amlan Ghosh , Jente B. Kuang
IPC分类号： G11C7/12
CPC分类号： G11C11/412 , G11C7/067
摘要： A sense amplifier is provided that comprises, responsive to receiving a set signal to turn on a set device and a precharged voltage level read bit line signal, a keeper device that turns on responsive to receiving a LOW signal from an inverting amplifier and pulls up the voltage at a first node so that a HIGH signal is output onto a global bit line. Responsive to receiving the set signal to turn on the set device and a read bit line signal that is discharging through a read stack path to ground and responsive to the read bit line signal discharging below a first predesigned voltage level, a read assist device in the sense amplifier turns on responsive to receiving a HIGH signal from the inverting amplifier and pulls down the voltage at the first node so that a LOW state is output onto a global bit line.
摘要翻译：提供了一种读出放大器，其包括响应于接收到设置信号以打开设备设备和预充电电压电平读取位线信号，保持器设备响应于从反相放大器接收低电平信号而接通，并且将上拉电压在第一节点处，使得HIGH信号被输出到全局位线。响应于接收所设置的信号以使所述设置装置和读取的位线信号通过读取堆叠路径放电到地并且响应于读取位线信号放电低于第一预先设计的电压电平，读取辅助装置在读出放大器响应于从反相放大器接收到高电平信号并且降低第一节点处的电压而导通，使得LOW状态输出到全局位线。

52. 发明授权

US08102194B2 Dual frequency divider having phase-shifted inputs and outputs 失效
标题翻译：双分频器具有相移输入和输出
公开(公告)号：US08102194B2
公开(公告)日：2012-01-24
申请号：US12860302
申请日：2010-08-20
申请人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
发明人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
IPC分类号： H03K3/01
CPC分类号： H02M3/073 , H02M2003/077 , H03L5/00
摘要： A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.
摘要翻译：分布式电荷泵系统使用延迟元件和分频器产生驱动不同电荷泵的异相泵浦时钟信号，以抵消每个电荷泵的峰值电流时钟边缘，从而降低总体峰值功率。时钟信号分频和相位偏移可以扩展到多个级别，以进一步平滑泵时钟信号转换。可以使用双分频器，其接收时钟信号及其补码，并产生相位差为90°的两个分频信号。在说明性实施例中，时钟发生器包括可变频率时钟源，并且电压调节器感测电荷泵的输出电压，基于当前选择的可变频率时钟源的频率产生参考电压，并暂时禁用当输出电压大于参考电压时，电荷泵（通过关闭本地泵浦时钟）。

53. 发明申请

US20110225438A1 COMPUTER PROGRAM PRODUCT FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES 有权
标题翻译：用于控制具有各元件选择电源电压的存储设备的计算机程序产品
公开(公告)号：US20110225438A1
公开(公告)日：2011-09-15
申请号：US13115149
申请日：2011-05-25
申请人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G06F1/32
CPC分类号： G11C11/417 , G11C5/14
摘要： A computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：用于使用每元件可选择的电源电压来控制存储设备的计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

54. 发明授权

US07994845B2 Switched-capacitor charge pumps 有权
标题翻译：开关电容充电泵
公开(公告)号：US07994845B2
公开(公告)日：2011-08-09
申请号：US12778960
申请日：2010-05-12
申请人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
发明人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
IPC分类号： G05F3/16 , G05F1/46 , H02M3/18
CPC分类号： H02M3/07 , G11C5/145 , G11C11/4074 , G11C2207/104
摘要： A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.
摘要翻译：开关电容器电荷泵包括两相充电电路，连接到开关电容器的输出节点的交叉耦合晶体管和连接到交叉耦合晶体管的源极端子的泵浦输出。电荷泵具有用于升压电荷转移的侧晶体管，并且侧晶体管的选通逻辑包括电平转换器，其控制与泵输出的连接或参考电压。提供负电荷泵和正电荷泵实施例。充电电路利用不重叠的宽和窄时钟信号来产生多个门控信号。泵时钟电路优选地提供宽和窄时钟信号的宽度的独立的可编程调整。可以使用将泵浦输出分流到开关电容器的第二节点的钳位电路来提供覆盖模式。

55. 发明申请

US20090129193A1 ENERGY EFFICIENT STORAGE DEVICE USING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES 失效
标题翻译：使用全能选择电源电压的能源效率存储设备
公开(公告)号：US20090129193A1
公开(公告)日：2009-05-21
申请号：US11941168
申请日：2007-11-16
申请人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B. Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C5/14 , G06F12/00
CPC分类号： G11C11/417 , G11C5/14
摘要： An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：使用每元件可选择的电源电压的节能存储装置在保持特定的性能水平的同时在存储装置中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

56. 发明申请

US20080122490A1 Circular Edge Detector 失效
标题翻译：圆形边缘检测器
公开(公告)号：US20080122490A1
公开(公告)日：2008-05-29
申请号：US11563888
申请日：2006-11-28
申请人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
发明人： Jerry C. Kao , Jente B. Kuang , Alan J. Drake , Gary D. Carpenter , Fadi H. Gebara
IPC分类号： H03K5/22
CPC分类号： H03K5/1534
摘要： A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.
摘要翻译：在包括多个边缘检测器单元的集成电路上的圆形边缘检测器，所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块，以及状态捕捉块可操作地连接以接收当前信元信号。将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个，作为用于下一个边缘检测器单元的先前单元信号，并且来自最后边沿的当前单元信号检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。

57. 发明授权

US6160292A Circuit and methods to improve the operation of SOI devices 失效
标题翻译：电路和方法来改善SOI器件的运行
公开(公告)号：US6160292A
公开(公告)日：2000-12-12
申请号：US63823
申请日：1998-04-22
申请人： Roy Childs Flaker, deceased , Louis L. Hsu , Jente B. Kuang
发明人： Roy Childs Flaker, deceased , Louis L. Hsu , Jente B. Kuang
IPC分类号： G11C16/08 , H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： G11C16/08 , H01L27/1203
摘要： According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable Vt effect is preserved. The overall body resistance of the individual devices has a minimal effect on the device body potential.
摘要翻译：根据本发明，公开了一种用于增强SOI制造器件的操作的电路和方法。在本发明的优选实施例中，提供了一种脉冲放电电路。这里，电路被设计成提供脉冲，其将在第一访问周期之前将存储器子阵列中的SOI器件的体上的累积电荷放电。如上所述，一旦累积的电荷已经耗散，则消除或大大降低了对存储器子阵列的连续访问的速度损失。利用适当的控制信号，时序和尺寸，这可以成为解决与SOI负载效应相关的问题的非常有效的方法。或者，代替将存储器电路中的所有SOI器件的主体连接到地，可以将本地字线驱动器的N沟道FET下拉器件的主体选择性地连接到参考地。这将使电路能够在克服上述负载问题的同时保留与SOI器件相关联的大部分速度优势。利用本发明的这个优选实施例，由双极负载效应引起的主要延迟最小化，同时保持由于提供较低的可变Vt效应引起的速度优势。各个器件的整体体电阻对器件的电位影响最小。

58. 发明授权

US6151200A Method of discharging SOI floating body charge 失效
标题翻译：放电SOI浮体电荷的方法
公开(公告)号：US6151200A
公开(公告)日：2000-11-21
申请号：US452934
申请日：1999-12-02
申请人： Louis L. Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary J. Saccamango
发明人： Louis L. Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary J. Saccamango
IPC分类号： H02H9/04 , H02H9/00
CPC分类号： H02H9/046
摘要： Apparatus and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances.
摘要翻译：通过第一和第二放电电路对被监测的SOI器件的体放电的装置和方法。当所监视的SOI器件的体电位处于使得所监视的SOI器件的体电量在正常工作周期时间容限内不能通过第一放电电路完全放电的水平时，选择性地激活第二放电电路。

59. 发明授权

US08214777B2 On-chip leakage current modeling and measurement circuit 有权
标题翻译：片内漏电流建模与测量电路
公开(公告)号：US08214777B2
公开(公告)日：2012-07-03
申请号：US12419377
申请日：2009-04-07
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Sani R. Nassif
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G01R31/025 , G11C29/006 , G11C29/028 , G11C29/50 , G11C2029/5006 , G11C2029/5602
摘要： A leakage current monitor circuit provides an accurate statistically representative analog of true off-state leakage current in a digital circuit integrated on a die. At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.
摘要翻译：泄漏电流监测电路在集成在管芯上的数字电路中提供精确的统计代表性的真实截止漏电流的模拟。与数字电路分离的至少一个N型晶体管和至少一个P型晶体管的尺寸被设计为表示数字电路中相应类型晶体管的总面积。 N型晶体管和P型晶体管的栅极根据数字电路的对应截止状态逻辑电平设置为电压。 N型和P型晶体管形成对应的电流镜电路的一部分，其可以向泄漏电流监视器和/或诸如比较器的控制电路提供输出，所述比较器确定N型或P-型晶体管的漏电流，类型设备已超过阈值。测量/控制电路的输出可用于确定集成电路的数字电路或系统环境的温度和/或控制操作。

60. 发明授权

US08138820B2 Peak power reduction methods in distributed charge pump systems 失效
标题翻译：分布式电荷泵系统的峰值功率降低方法
公开(公告)号：US08138820B2
公开(公告)日：2012-03-20
申请号：US13101139
申请日：2011-05-05
申请人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
发明人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
IPC分类号： H03K3/01
CPC分类号： H02M3/073 , H02M2003/077 , H03L5/00
摘要： A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.
摘要翻译：分布式电荷泵系统使用延迟元件和分频器产生驱动不同电荷泵的异相泵浦时钟信号，以抵消每个电荷泵的峰值电流时钟边缘，从而降低总体峰值功率。时钟信号分频和相位偏移可以扩展到多个级别，以进一步平滑泵时钟信号转换。可以使用双分频器，其接收时钟信号及其补码，并产生相位差为90°的两个分频信号。在说明性实施例中，时钟发生器包括可变频率时钟源，并且电压调节器感测电荷泵的输出电压，基于当前选择的可变频率时钟源的频率产生参考电压，并暂时禁用当输出电压大于参考电压时，电荷泵（通过关闭本地泵浦时钟）。

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