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51. 发明授权

US07446410B2 Circuit module with thermal casing systems 有权
标题翻译：具有热套管系统的电路模块
公开(公告)号：US07446410B2
公开(公告)日：2008-11-04
申请号：US11283355
申请日：2005-11-18
申请人： James Douglas Wehrly, Jr. , James Wilder , Mark Wolfe , Paul Goodwin
发明人： James Douglas Wehrly, Jr. , James Wilder , Mark Wolfe , Paul Goodwin
IPC分类号： H01L23/34 , H01L21/00 , H05K7/20
CPC分类号： H05K1/189 , H05K1/0203 , H05K3/0061 , H05K2201/056 , H05K2201/09445 , H05K2201/10159 , H05K2201/1056 , H05K2201/10734 , H05K2203/1572
摘要： Flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of major sides. Contacts are distributed along the flexible circuitry to provide connection between the module and an application environment. The populated flexible circuitry is disposed about an edge of a rigid substrate thus placing the integrated circuitry on one or both sides of the substrate with one or more layers of integrated circuitry on one or both sides of the substrate. The substrate form is preferably devised from thermally-conductive materials and one or more thermal spreaders are disposed in thermal contact with at least some of the constituent integrated circuitry of the module. Optionally, as an additional thermal management feature, the module may include a high thermal conductivity thermal sink or area that is disposed proximal to higher thermal energy IC devices. In preferred embodiments, extensions from the substrate body or substrate core encourage reduced thermal variations amongst the ICs of the module while providing an enlarged surface for shedding thermal energy from the module.
摘要翻译：灵活的电路装有沿主要侧面或两侧设置的集成电路（IC）。触点沿柔性电路分布，以提供模块与应用环境之间的连接。填充的柔性电路围绕刚性衬底的边缘设置，从而将集成电路放置在衬底的一侧或两侧上，在衬底的一侧或两侧上具有一层或多层集成电路。衬底形式优选地由导热材料设计，并且一个或多个热扩散器设置成与模块的组成集成电路中的至少一些热接触。可选地，作为附加的热管理特征，模块可以包括设置在较高热能IC器件附近的高导热性散热器或区域。在优选实施例中，来自衬底主体或衬底芯的延伸部促进模块的IC之间的热变化减小，同时提供用于从模块中排出热能的扩大表面。

52. 发明授权

US07335975B2 Integrated circuit stacking system and method 有权
标题翻译：集成电路堆叠系统及方法
公开(公告)号：US07335975B2
公开(公告)日：2008-02-26
申请号：US10958934
申请日：2004-10-05
申请人： James W. Cady , James Wilder , David L. Roper , Russell Rapport , James Douglas Wehrly, Jr. , Jeffrey Alan Buchle
发明人： James W. Cady , James Wilder , David L. Roper , Russell Rapport , James Douglas Wehrly, Jr. , Jeffrey Alan Buchle
IPC分类号： H01L23/48
CPC分类号： H01L23/49816 , H01L23/3114 , H01L23/49827 , H01L23/4985 , H01L23/5387 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/107 , H01L2225/1094 , H01L2924/19041 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2924/00012
摘要： The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP and a support element CSP are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. The flex circuit connects the ICs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).
摘要翻译：本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。本发明提供了用于将芯片级封装集成电路（CSP）或具有其他CSP的引线封装或者将单片或堆叠引线封装集成到节省PWB或其他板表面积的模块中的技术和结构。本发明可以利用各种尺寸和配置的封装，其范围从具有许多触点的较大封装的基底元件到较小的封装，例如诸如DSBGA的裸片尺寸的封装。在根据本发明设计的优选实施例中，基体元件CSP和支撑元件CSP通过具有图案化以选择性地连接两个CSP元件的至少两个导电层的柔性电路聚集。柔性电路连接IC，并在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。

53. 发明授权

US06956284B2 Integrated circuit stacking system and method 有权
标题翻译：集成电路堆叠系统及方法
公开(公告)号：US06956284B2
公开(公告)日：2005-10-18
申请号：US10814532
申请日：2004-03-31
申请人： James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
发明人： James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
IPC分类号： H01L23/02 , H01L23/31 , H01L23/367 , H01L23/498 , H01L23/538 , H01L25/10 , H05K1/14 , H05K1/18 , H05K3/36
CPC分类号： H01L23/3114 , H01L23/4985 , H01L23/5386 , H01L23/5387 , H01L25/105 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2225/06586 , H01L2225/06589 , H01L2225/107 , H01L2924/00014 , H01L2924/01055 , H01L2924/3011 , H05K1/141 , H05K1/147 , H05K1/189 , H05K3/363 , H05K2201/056 , H05K2201/10689 , H05K2201/10734 , H01L2224/16225 , H01L2924/00012 , H01L2224/0401
摘要： The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard may include a heat spreader portion with mounting feet. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.
摘要翻译：本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。在根据本发明的优选实施例中，形式标准提供了一种物理形式，其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。在替代实施例中，形式标准可以包括具有安装支脚的散热器部分。在存储器寻址系统的优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载影响。

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