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51. 发明授权

US06931493B2 Implementation of an LRU and MRU algorithm in a partitioned cache 有权
标题翻译：在分区缓存中实现LRU和MRU算法
公开(公告)号：US06931493B2
公开(公告)日：2005-08-16
申请号：US10346294
申请日：2003-01-16
申请人： Charles Ray Johns , James Allan Kahle , Peichun Peter Liu
发明人： Charles Ray Johns , James Allan Kahle , Peichun Peter Liu
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F12/123 , G06F12/128
摘要： The present invention provides for determining an MRU or LRU way of a partitioned cache. The partitioned cache has a plurality of ways. There are a plurality of partitions, each partition comprising at least one way. An updater is employable to update a logic table as a function of an access of a way. Partition comparison logic is employable to determine whether two ways are members of the same partition, and to allow the comparison of the ways correlating to a first matrix indices and a second matrix indices. An intersection generator is employable to create an intersection box of the memory table as a function of a first and second matrix indices. Access order logic is employable to combine the output of the intersection generator, thereby determining which way is the most or least recently used way.
摘要翻译：本发明提供用于确定分区高速缓存的MRU或LRU方式。分区缓存具有多种方式。存在多个分区，每个分区包括至少一个方式。更新器可用于根据方式的访问来更新逻辑表。分区比较逻辑可用于确定两种方式是否是相同分区的成员，并且允许比较与第一矩阵索引和第二矩阵索引相关的方式。交叉点生成器可用于根据第一和第二矩阵索引创建存储表的交集框。访问顺序逻辑可用于组合交叉发生器的输出，从而确定哪种方式是最近或最近最少使用的方式。

52. 发明授权

US06785841B2 Processor with redundant logic 失效
标题翻译：具有冗余逻辑的处理器
公开(公告)号：US06785841B2
公开(公告)日：2004-08-31
申请号：US09734371
申请日：2000-12-14
申请人： Chekib Akrout , Harm Peter Hofstee , James Allan Kahle
发明人： Chekib Akrout , Harm Peter Hofstee , James Allan Kahle
IPC分类号： G06F1100
CPC分类号： G06F11/2043 , G06F11/2028 , G06F11/2038
摘要： A system including a central processor and a plurality of attached processors all on a single die are disclosed. Each of the attached processors is preferably functionally equivalent to each of the other attached processors. The system further includes at least one redundant processor that is connectable to the central processor. The redundant processor may be substantially equivalent to each of the attached processors. Upon detecting a failure in one of the attached processors, the system is configured to disable the non-functional processor and enable the redundant processor. The attached processors may be connected to a memory interface unit via a parallel bus or a pipelined bus in which each attached processor is connected to a stage of the pipelined bus. The attached processors may each include a load/store unit and logic suitable for performing a mathematical function.
摘要翻译：公开了一种包括中央处理器和多个附属处理器的系统，其全部在单个管芯上。每个连接的处理器优选地在功能上等同于其他附加处理器中的每一个。该系统还包括可连接到中央处理器的至少一个冗余处理器。冗余处理器可以基本上等同于附接的每个处理器。一旦检测到所附加的处理器之一的故障，则该系统被配置为禁用非功能处理器并启用冗余处理器。连接的处理器可以经由并行总线或流水线总线连接到存储器接口单元，其中每个连接的处理器连接到流水线总线的级。附加的处理器可以各自包括适于执行数学功能的加载/存储单元和逻辑。

53. 发明授权

US06460115B1 System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanism 有权
标题翻译：用于将数据预取到多级缓存的系统和方法，包括选择性地使用软件提示来覆盖硬件预取机制
公开(公告)号：US06460115B1
公开(公告)日：2002-10-01
申请号：US09435865
申请日：1999-11-08
申请人： James Allan Kahle , Michael John Mayfield , Francis Patrick O'Connell , David Scott Ray , Edward John Silha , Joel Tendler
发明人： James Allan Kahle , Michael John Mayfield , Francis Patrick O'Connell , David Scott Ray , Edward John Silha , Joel Tendler
IPC分类号： G06F1300
CPC分类号： G06F9/3802 , G06F9/30047 , G06F9/383 , G06F12/0862 , G06F12/0897 , G06F2212/6028
摘要： A data processing system and method for prefetching data in a multi-level code subsystem. The data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache, and a third level cache and a system memory. Prefetching of cache lines is concurrently performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches are performed over a private or dedicated prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction or hint may be used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine.
摘要翻译：一种用于在多级代码子系统中预取数据的数据处理系统和方法。数据处理系统包括具有第一级高速缓存和预取引擎的处理器。耦合到处理器的是第二级缓存，以及第三级缓存和系统存储器。通过预取引擎将高速缓存行预取同时执行到第一，第二和第三级高速缓存中的每一个。从预取引擎到第二级和第三级高速缓存的预取请求通过私有或专用预取请求总线执行，该专用或专用预取请求总线与将数据从各种高速缓存级别传送到处理器的总线系统分开。软件指令或提示可用于通过覆盖硬件预取引擎的正常功能来加速预取过程。

54. 发明授权

US5926628A Selectable priority bus arbitration scheme 失效
标题翻译：可选优先级总线仲裁方案
公开(公告)号：US5926628A
公开(公告)日：1999-07-20
申请号：US892723
申请日：1997-07-15
申请人： Cang Ngoc Tran , James Allan Kahle
发明人： Cang Ngoc Tran , James Allan Kahle
IPC分类号： G06F13/364 , G06F13/36
CPC分类号： G06F13/364
摘要： A method and system for arbitrating access to a component of a computer have been disclosed the method and system include an arbitration unit for granting access to the component; and a plurality of units for executing a plurality of transactions requiring access to the component. Each transaction of the plurality of transactions has an encoded priority. Each of the plurality of units further provide the arbitration unit with the encoded priority of each of the plurality of transactions. The arbitration unit grants a predetermined number of the plurality of units access to the component in response to the encoded priority of each of the predetermined plurality of transactions.
摘要翻译：已经公开了一种用于仲裁对计算机的组件的访问的方法和系统，所述方法和系统包括用于授予访问组件的仲裁单元; 以及用于执行需要访问该组件的多个事务的多个单元。多个事务的每个事务具有编码的优先级。多个单元中的每一个还向仲裁单元提供多个交易中的每一个的编码优先级。仲裁单元响应于每个预定多个事务的编码优先级，向该组件授予多个单元的预定数量的访问。

55. 发明授权

US5913044A Method and system for simultaneous variable-width bus access in a multiprocessor system 失效
标题翻译：在多处理器系统中同时进行可变宽度总线访问的方法和系统
公开(公告)号：US5913044A
公开(公告)日：1999-06-15
申请号：US933154
申请日：1997-09-18
申请人： Cang Ngoc Tran , James Allan Kahle
发明人： Cang Ngoc Tran , James Allan Kahle
IPC分类号： G06F13/364 , G06F13/14 , G06F13/00
CPC分类号： G06F13/364
摘要： A method and system for enhanced bus access in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously. In response to one or more pending transactions, each processor outputs a request to bus arbitration logic for a maximum-permitted number of sub-buses. If the number of sub-buses granted to a particular processor equals the number of pending transactions at that processor, all pending transactions are performed in parallel on separate sub-buses. If the number of sub-buses granted is less than the number of pending transactions, pending transactions are performed in a priority order. Finally, if the number of granted sub-buses is greater than the number of pending transactions, selected transactions are performed over multiple sub-buses in parallel, greatly enhancing the speed of those transactions.
摘要翻译：一种在具有通过公共宽总线耦合到系统存储器的多处理器的多处理器系统中用于增强总线访问的方法和系统。公共宽总线被细分为多个子总线，其可以由所选择的处理器单独或分组访问，或者各个子总线可以由多个处理器同时访问。响应于一个或多个待处理的事务，每个处理器输出对总线仲裁逻辑的请求以允许最大允许数量的子总线。如果授予特定处理器的子总线数量等于该处理器中未决事务的数量，则所有挂起的事务将在单独的子总线上并行执行。如果授权的子总线数量少于待处理的事务数量，则按优先级顺序执行待处理事务。最后，如果授权子总线的数量大于未决事务的数量，则选择的事务并行执行多个子总线，大大提高了这些事务的速度。

56. 发明授权

US5748938A System and method for maintaining coherency of information transferred between multiple devices 失效
标题翻译：用于维护在多个设备之间传送的信息的一致性的系统和方法
公开(公告)号：US5748938A
公开(公告)日：1998-05-05
申请号：US350399
申请日：1994-12-06
申请人： James Allan Kahle
发明人： James Allan Kahle
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0835
摘要： A method and system are provided for maintaining memory coherency. A first device stores information. A second device is coupled to the first device. The second device inputs at least a portion of the information and outputs an indication that the portion is not to be cached by the second device. Rather than initializing other devices to "know" in advance that a cache memory is absent from a given device, a control signal indicates the device's intent to not cache the requested portion of information in a cache memory.
摘要翻译：提供了一种用于维持存储器一致性的方法和系统。第一个设备存储信息。第二设备耦合到第一设备。第二设备输入信息的至少一部分并输出该部分不被第二设备高速缓存的指示。事先将其他设备初始化为“知道”，从给定设备中不存在高速缓冲存储器，控制信号指示设备不希望将所请求的部分信息缓存在高速缓冲存储器中的意图。

57. 发明授权

US5715420A Method and system for efficient memory management in a data processing system utilizing a dual mode translation lookaside buffer 失效
标题翻译：在利用双模式翻转后备缓冲器的数据处理系统中有效的存储器管理的方法和系统
公开(公告)号：US5715420A
公开(公告)日：1998-02-03
申请号：US387147
申请日：1995-02-10
申请人： James Allan Kahle , Albert J. Loper , Aubrey Deene Ogden , John Victor Sell , Gregory L. Limes
发明人： James Allan Kahle , Albert J. Loper , Aubrey Deene Ogden , John Victor Sell , Gregory L. Limes
IPC分类号： G06F12/10 , G06F12/14 , G06F21/02 , G06F12/00
CPC分类号： G06F12/145 , G06F12/1027
摘要： A method and system for efficient memory management in a data processing system which utilizes a memory management unit to translate effective addresses into real addresses within a translation lookaside buffer is disclosed. During a first mode of operation a selected number of effective address identifiers are stored in the translation lookaside buffer. In association with each virtual address identifier is a corresponding real address entry for a single memory block wherein selected virtual addresses may be translated into corresponding real addresses utilizing the translation lookaside buffer. In a second mode of operation, a selected number of virtual address identifiers are stored in a translation lookaside buffer and each virtual address identifier has a number of protection bits stored in association therewith, wherein each protection bit is indicative of a protection status for a large number of contiguous memory blocks beginning with the associated virtual address identifier, wherein memory block protection may be provided for a large number of memory blocks utilizing a fixed size translation lookaside buffer.
摘要翻译：公开了一种在数据处理系统中有效地进行存储器管理的方法和系统，其利用存储器管理单元将有效地址转换为翻译后备缓冲器内的实际地址。在第一操作模式期间，选择数量的有效地址标识符被存储在转换后备缓冲器中。与每个虚拟地址标识符相关联的是用于单个存储器块的对应的实际地址条目，其中所选择的虚拟地址可以使用转换后备缓冲器被转换成相应的实际地址。在第二操作模式中，选择数量的虚拟地址标识符被存储在转换后备缓冲器中，并且每个虚拟地址标识符具有与其相关联地存储的多个保护位，其中每个保护位指示大的保护位的保护状态以相关联的虚拟地址标识符开始的连续存储器块的数量，其中可以使用固定尺寸的转换后备缓冲器为大量存储器块提供存储块保护。

58. 发明授权

US08108564B2 System and method for a configurable interface controller 有权
标题翻译：可配置接口控制器的系统和方法
公开(公告)号：US08108564B2
公开(公告)日：2012-01-31
申请号：US10697903
申请日：2003-10-30
申请人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
发明人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F3/00
CPC分类号： G06F3/1423 , G06F3/1454 , G09G5/14 , G09G2360/121 , G09G2370/04
摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.
摘要翻译：灵活的输入/输出控制器逻辑与现有的输入/输出控制器（IOC）进行接口，以便配置向国际奥委会发送和接收的数据量。灵活的I / O接口以特定组件确定的速率从组件接收数据。然后，灵活的I / O接口以适合于I / O控制器的速率将接收的数据馈送到传统的I / O控制器。因此，保持与各个I / O控制器的接口。灵活的I / O逻辑平衡多个独立I / O控制器之间的带宽，以便更好地利用整个系统I / O带宽。在一个实施例中，在系统构建期间确定由灵活I / O逻辑管理的I / O配置，而在另一实施例中，在系统初始化期间设置I / O配置。

59. 发明申请

US20100312969A1 Methods And Apparatus For Supporting Multiple Configurations In A Multi-Processor System 有权
标题翻译：在多处理器系统中支持多种配置的方法和装置
公开(公告)号：US20100312969A1
公开(公告)日：2010-12-09
申请号：US12858915
申请日：2010-08-18
申请人： Takeshi Yamazaki , Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
发明人： Takeshi Yamazaki , Scott Douglas Clark , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0815 , G06F12/0835
摘要： Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.
摘要翻译：方法和装置提供通过一个或多个可配置接口电路来互连一个或多个多处理器和一个或多个外部设备，其适于在以下操作中操作：（i）提供一致对称接口的第一模式; 或（ii）提供非相干界面的第二模式。

60. 发明授权

US07698473B2 Methods and apparatus for list transfers using DMA transfers in a multi-processor system 有权
标题翻译：在多处理器系统中使用DMA传输的列表传输的方法和装置
公开(公告)号：US07698473B2
公开(公告)日：2010-04-13
申请号：US11029891
申请日：2005-01-05
申请人： Takeshi Yamazaki , Tsutomu Horikawa , James Allan Kahle , Charles Ray Johns , Michael Norman Day , Peichun Peter Liu
发明人： Takeshi Yamazaki , Tsutomu Horikawa , James Allan Kahle , Charles Ray Johns , Michael Norman Day , Peichun Peter Liu
IPC分类号： G06F13/28 , G06F15/167
CPC分类号： G06F13/28 , Y02D10/14
摘要： Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the shared memory and the DMAC is operatively coupled to the local memory.
摘要翻译：方法和装置提供了响应于处理器向直接存储器访问控制器（DMAC）发出的单个DMA命令，在处理器的共享存储器和本地存储器之间传送多个数据块，其中处理器能够操作与共享存储器和DMAC的通信可操作地耦合到本地存储器。

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