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51. 发明申请

US20170084500A1 DUAL LINER SILICIDE 有权
公开(公告)号：US20170084500A1
公开(公告)日：2017-03-23
申请号：US15366223
申请日：2016-12-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc
发明人： Balasubramanian Pranatharthiharan , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/8238 , H01L27/092 , H01L23/522 , H01L29/66
CPC分类号： H01L21/823871 , H01L21/28518 , H01L21/76897 , H01L21/823814 , H01L21/823864 , H01L23/5226 , H01L27/092 , H01L29/0847 , H01L29/41725 , H01L29/456 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

52. 发明授权

US09564372B2 Dual liner silicide 有权
标题翻译：双衬里硅化物
公开(公告)号：US09564372B2
公开(公告)日：2017-02-07
申请号：US14740987
申请日：2015-06-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc
发明人： Balasubramanian Pranatharthiharan , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/82 , H01L21/8238 , H01L29/66 , H01L27/092 , H01L29/417
CPC分类号： H01L21/823871 , H01L21/28518 , H01L21/76897 , H01L21/823814 , H01L21/823864 , H01L23/5226 , H01L27/092 , H01L29/0847 , H01L29/41725 , H01L29/456 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.
摘要翻译：制造双硅化物器件的方法包括：生长用于N型器件的源极和漏极（S / D）区域，在栅极结构上形成保护层，并且在N型器件的S / D区域上生长S / D区域用于P型设备。第一电介质层被共形沉积，部分被去除以暴露S / D区域。用于P型器件的暴露的S / D区域被硅化以形成衬垫。第二电介质层被共形沉积。在第二电介质层上形成电介质填充物。接触孔通过第二介电层打开，露出P型器件的衬垫，露出N型器件的保护层。通过打开保护层来暴露N型器件的S / D区域。暴露的与栅极结构相邻的S / D区域被硅化以形成用于N型器件的衬垫。触点形成。

53. 发明申请

US20170033023A1 TEST STRUCTURE MACRO FOR MONITORING DIMENSIONS OF DEEP TRENCH ISOLATION REGIONS AND LOCAL TRENCH ISOLATION REGIONS 审中-公开
公开(公告)号：US20170033023A1
公开(公告)日：2017-02-02
申请号：US15292184
申请日：2016-10-13
申请人： International Business Machines Corporation , Globalfoundries, Inc.
发明人： Tenko Yamashita , Chun-Chen Yeh , Hui Zang
IPC分类号： H01L21/66 , H01L29/78 , H01L29/66 , H01L29/06
CPC分类号： H01L22/32 , H01L21/76895 , H01L22/12 , H01L22/14 , H01L22/20 , H01L22/34 , H01L23/5222 , H01L23/5226 , H01L23/528 , H01L29/0649 , H01L29/66545 , H01L29/7851
摘要： Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

54. 发明申请

US20160104644A1 PROCESS FOR INTEGRATED CIRCUIT FABRICATION INCLUDING A UNIFORM DEPTH TUNGSTEN RECESS TECHNIQUE 有权
标题翻译：集成电路制造工艺，包括均匀深度浸渍技术
公开(公告)号：US20160104644A1
公开(公告)日：2016-04-14
申请号：US14512700
申请日：2014-10-13
申请人： STMicroelectronics, Inc. , GlobalFoundries Inc , International Business Machines Corporation
发明人： Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/8234 , H01L29/423 , H01L27/088
CPC分类号： H01L29/42376 , H01L21/82345 , H01L21/823456 , H01L27/088 , H01L29/42372 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/66553 , H01L29/78
摘要： Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.
摘要翻译：从预金属层去除虚拟门以产生具有第一长度的第一开口和第二开口（具有长于第一长度的第二长度）。用于金属栅电极的功函数金属设置在第一和第二开口中。沉积钨以填充第一开口并保形地排列第二开口，从而留下第三个开口。钨层的厚度基本上等于第一开口的长度。第三个开口填充绝缘材料。然后使用干蚀刻将钨从第一和第二开口凹入到与金属前层的顶表面基本相同的深度以完成金属栅电极。然后在凹槽操作之后留下的开口填充有在包括金属栅电极的栅堆叠上形成盖的电介质材料。

55. 发明授权

US09159633B2 Test macro for use with a multi-patterning lithography process 有权
标题翻译：用于多图案化光刻工艺的测试宏
公开(公告)号：US09159633B2
公开(公告)日：2015-10-13
申请号：US14026172
申请日：2013-09-13
申请人： International Business Machines Corporation , GlobalFoundries, Inc.
发明人： Tenko Yamashita , Chun-Chen Yeh , Jin Cho , Hui Zang
IPC分类号： H01L23/58 , H01L29/10 , H01L21/66 , H01L21/8234
CPC分类号： H01L22/14 , G03F7/70466 , H01L21/823431 , H01L22/10 , H01L22/12 , H01L22/34
摘要： A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region and forming a first and second source/drain regions in the active area. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region. The method further includes determining if an overlay shift has occurred during the formation of the active area by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.
摘要翻译：提供了一种使用多重图案化光刻工艺（MPLP）形成具有测试宏的集成电路的方法。该方法包括形成具有第一和第二栅极区的测试宏的有源区，并在有源区中形成第一和第二源极/漏极区。该方法还包括形成连接到第一栅极区域的第一触点，连接到第二栅极区域的第二触点，连接到第一源极/漏极区域的第三触点和连接到源极/漏极区域的第四触点。该方法还包括通过测试第一接触，第二接触，第三接触或第四接触中的一个或多个之间的短路来确定在形成有源区域期间是否发生覆盖偏移。

56. 发明授权

US09082852B1 LDMOS FinFET device using a long channel region and method of manufacture 有权
标题翻译： LDMOS FinFET器件采用长沟道区和制造方法
公开(公告)号：US09082852B1
公开(公告)日：2015-07-14
申请号：US14560472
申请日：2014-12-04
申请人： STMicroelectronics, Inc. , International Business Machines Corporation , GlobalFoundries Inc
发明人： Qing Liu , Ruilong Xie , Xiuyu Cai , Chun-Chen Yeh
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： A FinFET includes a semiconductor fin supporting a first transistor and a second transistor. A first transistor gate electrode extends over a first channel region of the fin and a second transistor gate electrode extends over a second channel region of the fin. Epitaxial growth material on a top of the fin forms a raised source region on a first side of the first transistor gate electrode, an intermediate region between a second side of the first transistor gate electrode and a first side of the second transistor gate electrode, and a raised drain region on a second side of the second transistor gate electrode. The first and second transistor gate electrodes are short circuit connected to each other, with the first transistor configured to have a first threshold voltage and the second transistor configured to have a second threshold voltage different from the first threshold voltage.
摘要翻译： FinFET包括支撑第一晶体管和第二晶体管的半导体鳍片。第一晶体管栅极电极延伸在鳍片的第一沟道区域上，第二晶体管栅电极在鳍片的第二沟道区域上延伸。翅片顶部的外延生长材料在第一晶体管栅电极的第一侧上形成升高的源极区，在第一晶体管栅电极的第二侧和第二晶体管栅电极的第一侧之间的中间区域，以及在所述第二晶体管栅电极的第二侧上的升高的漏极区。第一和第二晶体管栅极彼此短路，其中第一晶体管被配置为具有第一阈值电压，并且第二晶体管被配置为具有不同于第一阈值电压的第二阈值电压。

57. 发明授权

US11562906B2 Low resistance source drain contact formation with trench metastable alloys and laser annealing 有权
公开(公告)号：US11562906B2
公开(公告)日：2023-01-24
申请号：US16265784
申请日：2019-02-01
申请人： International Business Machines Corporation , GLOBALFOUNDRIES Inc.
发明人： Oleg Gluschenkov , Zuoguang Liu , Shogo Mochizuki , Hiroaki Niimi , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L21/285 , H01L29/08 , H01L29/24 , H01L29/267 , H01L29/78 , H01L29/66 , H01L21/768
摘要： Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

58. 发明授权

US10593780B2 Forming replacement low-K spacer in tight pitch fin field effect transistors 有权
公开(公告)号：US10593780B2
公开(公告)日：2020-03-17
申请号：US15222261
申请日：2016-07-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES INC. , STMicroelectronics, Inc.
发明人： Xiuyu Cai , Chun-Chen Yeh , Qing Liu , Ruilong Xie
IPC分类号： H01L21/768 , H01L29/78 , H01L29/66 , H01L29/417 , H01L29/06 , H01L29/08 , H01L29/161 , H01L29/165
摘要： A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

59. 发明授权

US10304747B2 Dual liner silicide 有权
公开(公告)号：US10304747B2
公开(公告)日：2019-05-28
申请号：US15847028
申请日：2017-12-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc
发明人： Balasubramanian Pranatharthiharan , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L29/08 , H01L21/8238 , H01L29/66 , H01L27/092 , H01L29/417 , H01L29/45 , H01L23/522 , H01L21/768 , H01L21/285
摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

60. 发明授权

US09997418B2 Dual liner silicide 有权
公开(公告)号：US09997418B2
公开(公告)日：2018-06-12
申请号：US15240554
申请日：2016-08-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc
发明人： Balasubramanian Pranatharthiharan , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/8238 , H01L29/66 , H01L27/092 , H01L29/417 , H01L29/08 , H01L29/45 , H01L23/522 , H01L21/768 , H01L21/285
CPC分类号： H01L21/823871 , H01L21/28518 , H01L21/76897 , H01L21/823814 , H01L21/823864 , H01L23/5226 , H01L27/092 , H01L29/0847 , H01L29/41725 , H01L29/456 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

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