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51. 发明授权

US5410447A Portable computer comprising keyboard and coordinate input tablet connected by two perpendicularly arranged hinges 失效
标题翻译：便携式计算机包括由两个垂直排列的铰链连接的键盘和坐标输入板
公开(公告)号：US5410447A
公开(公告)日：1995-04-25
申请号：US114090
申请日：1993-08-31
申请人： Shigenori Miyagawa , Koichi Kobayashi , Shimpei Kunii , Shizuo Kamio , Hiroyuki Sakamoto , Fumitaka Sato , Ryoichi Ishiura
发明人： Shigenori Miyagawa , Koichi Kobayashi , Shimpei Kunii , Shizuo Kamio , Hiroyuki Sakamoto , Fumitaka Sato , Ryoichi Ishiura
IPC分类号： E05D11/08 , E05D15/58 , G06F1/16 , G06F3/033 , G06F3/048 , H05K7/16
CPC分类号： G06F1/1681 , G06F1/1618 , G06F1/162 , G06F1/1677 , G06F1/1679 , E05D11/087 , E05D15/582 , E05Y2900/606 , G06F2200/1614
摘要： A main body case for storing a keyboard and an upper case for storing an integrated display/input device are coupled by two hinge units arranged perpendicularly to one another to be arbitrarily pivotal from a state wherein the keyboard faces the integrated display/input device to a state wherein the back surfaces of the keyboard and the integrated display/input device face each other.
摘要翻译：用于存储键盘的主体壳体和用于存储集成显示/输入设备的上壳体通过彼此垂直布置的两个铰链单元联接，以从键盘面向集成显示/输入设备的状态任意地枢转到状态，其中键盘的背面和集成的显示/输入装置彼此面对。

52. 发明授权

US4943935A Apparatus and method for plotting curved figures represented by high order functions in a bit map 失效
标题翻译：用于绘制位图中由高阶函数表示的曲线图的装置和方法
公开(公告)号：US4943935A
公开(公告)日：1990-07-24
申请号：US248450
申请日：1988-09-23
申请人： Fumitaka Sato
发明人： Fumitaka Sato
IPC分类号： G06T11/20 , G09G5/393
CPC分类号： G06T11/203 , G09G5/393
摘要： A value of a parameter t corresponding to the adjacent next plot point on a bit map memory in an x or y direction is calculated, one of the x or y coordinate values of a current plot point is changed by 1 to calculate a coordinate in the same direction of the next plot point, and the other coordinate of the next plot point is calculated on the basis of an approximated parameter t and cubic curve, thereby plotting the next plot point on the bit map memory.
摘要翻译：计算对应于x或y方向上的位图存储器上的相邻下一个绘图点的参数t的值，将当前绘图点的x或y坐标值之一改变1以计算坐标根据近似参数t和三次曲线计算下一个绘图点的另一个坐标，从而绘制位图存储器上的下一个绘图点。

53. 发明授权

US4616331A Information processing system consisting of an arithmetic control unit formed into a one-chip typed by application of a highly-integrated semiconductor device 失效
标题翻译：信息处理系统由通过应用高度集成的半导体器件形成为单片的算术控制单元构成
公开(公告)号：US4616331A
公开(公告)日：1986-10-07
申请号：US236116
申请日：1981-02-19
申请人： Tsuneo Kinoshita , Fumitaka Sato , Isamu Yamazaki
发明人： Tsuneo Kinoshita , Fumitaka Sato , Isamu Yamazaki
IPC分类号： G06F9/38 , G06F9/30 , G06F13/00
CPC分类号： G06F9/3812 , G06F9/3802 , G06F9/3804
摘要： In a one-chip high density arithmetic control unit capable of prefetching user's instructions from main memory, an arithmetic logic unit (ALU) subtracts the contents of a location counter holding the address of the next instruction to be executed, from the contents of a memory address register holding an address into which data will be written. The difference is fed through the gates connected to the ALU for determining whether or not prefetched instructions will have to be refetched. An address matching mechanism provided outside the one-chip arithmetic control unit includes a comparator for comparing memory addresses to a preset execution stop address. The output signal of the comparator is stored in a memory section which is provided to correspond to the prefetched instruction buffer, and when an instruction stored in the prefetched instruction buffer is transferred to an instruction register, the signal stored in the corresponding memory section is also read out and used to determine whether to stop execution. Further, whenever access is made to main memory a signal indicating whether the access is legal is externally generated and may be stored in a second memory section. Like the address matching signal, this signal is read out when the corresponding instruction from the prefetched instruction buffer is transferred to the instruction register. An illegal address interruption is produced when this signal indicates that the address was illegal.
摘要翻译：在能够从主存储器预取用户指令的单芯片高密度算术控制单元中，算术逻辑单元（ALU）从存储器的内容中减去保持要执行的下一个指令的地址的位置计数器的内容地址寄存器保存写入数据的地址。差异通过连接到ALU的门馈送，以确定是否必须重新获取预取指令。在单芯片运算控制单元外提供的地址匹配机构包括比较器，用于将存储器地址与预设的执行停止地址进行比较。比较器的输出信号存储在与预取指令缓冲器相对应的存储器部分中，并且当存储在预取指令缓冲器中的指令被传送到指令寄存器时，存储在相应存储器部分中的信号也是读出并用于确定是否停止执行。此外，每当访问主存储器时，指示是否合法的信号是外部生成的，并且可以存储在第二存储器部分中。类似地址匹配信号，当来自预取指令缓冲器的相应指令被传送到指令寄存器时，该信号被读出。当该信号表示该地址是非法的时，产生非法地址中断。

54. 发明授权

US4453230A Address conversion system 失效
标题翻译：地址转换系统
公开(公告)号：US4453230A
公开(公告)日：1984-06-05
申请号：US390783
申请日：1982-06-21
申请人： Tetsuya Mizoguchi , Fumitaka Sato , Tadanobu Furukatsu
发明人： Tetsuya Mizoguchi , Fumitaka Sato , Tadanobu Furukatsu
IPC分类号： G06F12/10 , G06F13/00
CPC分类号： G06F12/1027
摘要： An address conversion system comprises an improved associative memory circuit for providing a real address corresponding to an applied virtual address with reference to the correspondence between virtual and real addresses stored in a main memory. The associative memory includes first and second memories for storing a part of the correspondence between virtual and real addresses. The second memory is essentially a set associative memory but is not connected with address comparators directly. The first memory is higher in speed but smaller in capacity than the second memory. When the first memory stores the correspondence between the virtual and real address corresponding to the applied virtual address, the real address corresponding to the applied virtual address is immediately delivered.
摘要翻译：地址转换系统包括改进的关联存储器电路，用于参考存储在主存储器中的虚拟地址和实际地址之间的对应关系来提供与所应用的虚拟地址相对应的实际地址。关联存储器包括用于存储虚拟地址和实际地址之间对应关系的一部分的第一和第二存储器。第二个存储器本质上是一个集合的联想存储器，但是不直接与地址比较器连接。第一个存储器的速度较高，但容量小于第二个存储器。当第一存储器存储与应用的虚拟地址相对应的虚拟地址和实际地址之间的对应关系时，立即传送与应用的虚拟地址相对应的实际地址。

55. 发明授权

US4354258A Memory board automatically assigned its address range by its position 失效
标题翻译：内存板通过其位置自动分配地址范围
公开(公告)号：US4354258A
公开(公告)日：1982-10-12
申请号：US120469
申请日：1980-02-11
申请人： Fumitaka Sato
发明人： Fumitaka Sato
IPC分类号： G06F12/06 , G11C8/12 , G11C8/00
CPC分类号： G11C8/12 , G06F12/0676
摘要： A subtractor circuit subtracts start address information supplied from address information to produce a logical address. An adder circuit adds the start address information to memory capacity information to form the start address of the succeeding memory board. When 0.ltoreq.output information from the subtraction circuit
摘要翻译：减法器电路减去从地址信息提供的起始地址信息以产生逻辑地址。加法器电路将起始地址信息添加到存储器容量信息以形成后续存储器板的起始地址。当0

56. 发明授权

US4212059A Information processing system 失效
标题翻译：信息处理系统
公开(公告)号：US4212059A
公开(公告)日：1980-07-08
申请号：US886598
申请日：1978-03-14
申请人： Fumitaka Sato , Masahiko Iwane , Masaki Murayama
发明人： Fumitaka Sato , Masahiko Iwane , Masaki Murayama
IPC分类号： G06F11/267 , G06F11/273 , G06F11/00
CPC分类号： G06F11/2236 , G06F11/2736
摘要： An information processing system includes an information processing unit and an operation console. The information processing unit includes a CPU having a fault diagnostic unit which is coupled with the diagnostic interface port of the operation console, through a diagnostic interface. The operation console is provided with a microprocessor having a first operation mode carrying out at least a normal operation processing function and a second mode executing both a maintenance command processing function and a normal operation processing function, and with a memory for storing a maintenance command processing routine for executing the maintenance command processing function. When an operator issues an instruction for shifting the first operation mode to the second operation mode control is transferred to the operation console so that the microprocessor executes the maintenance command processing function and the normal operation processing function.
摘要翻译：信息处理系统包括信息处理单元和操作控制台。信息处理单元包括具有通过诊断接口与操作控制台的诊断接口端口耦合的故障诊断单元的CPU。操作控制台设置有具有执行至少正常操作处理功能的第一操作模式和执行维护命令处理功能和正常操作处理功能的第二模式的微处理器，以及用于存储维护命令处理的存储器执行维护命令处理功能的程序。当操作者发出用于将第一操作模式转换到第二操作模式的指令时，将控制转移到操作控制台，使得微处理器执行维护命令处理功能和正常操作处理功能。

57. 发明申请

US20110208525A1 VOICE RECOGNIZING APPARATUS 有权
标题翻译：语音识别装置
公开(公告)号：US20110208525A1
公开(公告)日：2011-08-25
申请号：US12599217
申请日：2008-03-27
申请人： Yuzuru Inoue , Tadashi Suzuki , Fumitaka Sato , Takayoshi Chikuri
发明人： Yuzuru Inoue , Tadashi Suzuki , Fumitaka Sato , Takayoshi Chikuri
IPC分类号： G10L15/02
CPC分类号： G10L15/22
摘要： A voice recognizing apparatus includes a voice start instructing section 3 for instructing to start voice recognition; a voice input section 1 for receiving uttered voice and converting to a voice signal; a voice recognizing section 2 for recognizing the voice on the basis of the voice signal; an utterance start time detecting section 4 for detecting duration from the time when the voice start instructing section instructs to the time when the voice input section delivers the voice signal; an utterance timing deciding section 5 for deciding utterance timing indicating whether the utterance start is quick or slow by comparing the duration detected by the utterance start time detecting section with a prescribed threshold; an interaction control section 6 for determining a content, which is to be shown when exhibiting a recognition result of the voice recognizing section, in accordance with the utterance timing decided; a system response generating section 7 for generating a system response on the basis of the determined content to be shown; and an output section 8 and 9 for outputting the system response generated.
摘要翻译：语音识别装置包括：语音开始指示部分3，用于指示开始语音识别; 语音输入部分1，用于接收发出的语音并转换成语音信号; 语音识别部分2，用于基于语音信号识别语音; 发声开始时间检测部分4，用于从话音开始指示部分指示时间到语音输入部分传送语音信号的时间检测持续时间; 发声定时决定部5，用于通过将由发音开始时间检测部检测出的持续时间与规定的阈值进行比较来判定表示发音开始是快还是慢的发声定时; 一个交互控制部分6，用于根据确定的话语时间来确定呈现语音识别部分的识别结果时要显示的内容; 系统响应产生部分7，用于根据所确定的要显示的内容产生系统响应; 以及用于输出所生成的系统响应的输出部分8和9。

58. 发明授权

US07533278B2 Electronic device and power saving control method 失效
标题翻译：电子设备和省电控制方法
公开(公告)号：US07533278B2
公开(公告)日：2009-05-12
申请号：US11341998
申请日：2006-01-27
申请人： Shogo Maeshima , Fumitaka Sato
发明人： Shogo Maeshima , Fumitaka Sato
IPC分类号： G06F1/20 , G06F1/32
CPC分类号： G06F1/203 , G06F1/206 , G06F1/3203 , Y02D10/16
摘要： According to one embodiment, an EC/KBC reads data of an acceleration sensor. The EC/KBC determines whether a computer is in a top heat state. If the EC/KBC determines that the computer is in the top heat state, it notifies a BIOS stored in a BIOS-ROM of a message to this effect. The BIOS which is notified from the EC/KBC that the computer is in the top heat state notifies an OS (Operating System) of the message to this effect. The OS sets a CPU to a power saving mode by an existing means such as the power saving utility of the OS, and sets the computer to the power saving mode.
摘要翻译：根据一个实施例，EC / KBC读取加速度传感器的数据。 EC / KBC确定计算机是否处于最高热状态。如果EC / KBC确定计算机处于最高热状态，则会通知存储在BIOS-ROM中的BIOS的消息，从而达到此目的。从EC / KBC通知计算机处于最高热状态的BIOS通知该消息的OS（操作系统）。 OS通过诸如OS的省电实用程序等现有手段将CPU设置为省电模式，并将计算机设置为省电模式。

59. 发明授权

US07231642B2 Vehicle-mounted multimedia device 有权
标题翻译：车载多媒体设备
公开(公告)号：US07231642B2
公开(公告)日：2007-06-12
申请号：US10275622
申请日：2001-03-19
申请人： Shinichiro Araki , Minoru Yoshida , Akio Uekawa , Yosuke Asai , Mitsuo Shimotani , Fumitaka Sato
发明人： Shinichiro Araki , Minoru Yoshida , Akio Uekawa , Yosuke Asai , Mitsuo Shimotani , Fumitaka Sato
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： G06F9/46
摘要： An on-vehicle multimedia device to be operated by software 16 including an application module group 18 having a plurality of application modules 19 that realizes their respective different functions and an application control module 17 for controlling each of the application modules 19, characterized by the device comprising external hardware which inputs and outputs data to be processed by the software.
摘要翻译：一种由软件16操作的车载多媒体设备，包括具有实现各自不同功能的多个应用模块19的应用模块组18和用于控制每个应用模块19的应用控制模块19，其特征在于该设备包括输入和输出要由软件处理的数据的外部硬件。

60. 发明授权

US06470089B2 Data recording/reproducing apparatus, data recording/reproducing method applied to the apparatus, and computer program product used in data processing apparatus 失效
标题翻译：数据记录/再现装置，应用于该装置的数据记录/再现方法，以及在数据处理装置中使用的计算机程序产品
公开(公告)号：US06470089B2
公开(公告)日：2002-10-22
申请号：US09905112
申请日：2001-07-16
申请人： Seigo Ito , Yasuhiro Ishibashi , Fumitaka Sato
发明人： Seigo Ito , Yasuhiro Ishibashi , Fumitaka Sato
IPC分类号： G06K900
CPC分类号： H04N5/76 , G11B20/00086 , G11B20/1879 , H04N5/781 , H04N5/85 , H04N9/8205
摘要： In a data recording and reproducing apparatus which records and reproduces a record medium in which at least two kinds of data having different data types can be recorded, data is read out from the record medium, and a digital watermark is detected from the data read out. The kind of data is determined depending upon whether the digital watermark is detected, and it is determined whether retry processing at the time of reading-out the data and verifying processing at the time of writing should be executed. The retry processing or the verifying processing is executed only for the data which is determined that the retry processing or the verifying processing should be executed. Therefore, in the case of data whose reading-out continuity is more important than reliability, the retry processing is omitted, so that time required for reading-out processing can be shortened. In the case of data whose recording continuity is more important than reliability, the verifying processing is omitted, so that time required for writing processing can be shortened.
摘要翻译：在记录和再现其中可以记录具有不同数据类型的至少两种数据的记录介质的数据记录和再现装置中，从记录介质读出数据，并从读出的数据中检测出数字水印。数据的种类根据是否检测到数字水印来确定，并且确定是否应当执行读取数据时的重试处理和写入时的验证处理。对于确定应该执行重试处理或验证处理的数据，执行重试处理或验证处理。因此，在读出连续性比可靠性更重要的数据的情况下，省略重试处理，可以缩短读出处理所需的时间。在其记录连续性比可靠性更重要的数据的情况下，省略了验证处理，从而可以缩短写入处理所需的时间。

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