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51. 发明授权

US08432750B2 Non-volatile memory systems and methods including page read and/or configuration features 有权
标题翻译：非易失性存储器系统和方法，包括页面读取和/或配置特征
公开(公告)号：US08432750B2
公开(公告)日：2013-04-30
申请号：US12961458
申请日：2010-12-06
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

52. 发明授权

US08300494B2 Sub volt flash memory system 有权
标题翻译：亚伏闪存系统
公开(公告)号：US08300494B2
公开(公告)日：2012-10-30
申请号：US12980209
申请日：2010-12-28
申请人： Hieu Van Tran , Sang T. Nguyen , Anh Ly , Hung Q. Nguyen
发明人： Hieu Van Tran , Sang T. Nguyen , Anh Ly , Hung Q. Nguyen
IPC分类号： G11C8/00
CPC分类号： G11C16/28 , G11C16/08 , G11C16/30
摘要： Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.
摘要翻译：各种电路包括具有用于接收不同于电源电压和接地的体电压的体电压端子的MOS晶体管。可以选择性地设置体电压，使得一些MOS晶体管具有设置为电源电压或地的体电压，并且其它MOS晶体管具有不同的体电压。体电压可以被设置为MOS晶体管中的正向或反向偏置pn结。各种电路包括比较器，运算放大器，感测电路，解码电路和其它电路。电路可以包括在存储器系统中。

53. 发明授权

US08232833B2 Charge pump systems and methods 有权
标题翻译：电荷泵系统和方法
公开(公告)号：US08232833B2
公开(公告)日：2012-07-31
申请号：US11805765
申请日：2007-05-23
申请人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
发明人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
IPC分类号： G05F3/24 , H02M3/18
CPC分类号： G05F3/02 , H02M3/073 , H02M2001/322
摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
摘要翻译：数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。电荷泵可以包括多个泵级。示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲，预充电电路。

54. 发明授权

US08154928B2 Integrated flash memory systems and methods for load compensation 有权
标题翻译：集成闪存系统和负载补偿方法
公开(公告)号：US08154928B2
公开(公告)日：2012-04-10
申请号：US12947719
申请日：2010-11-16
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation.
摘要翻译：公开了系统和方法，其包括补偿存储器阵列中使用的电源电压的幅度变化的特征。根据一些方面，补偿电路可以为数据列提供可调谐的限流负载，其中可以调整负载来动态补偿电源电压的变化。在某些方面，补偿电路可以采用配置为电压跟随器的运算放大器。电压跟随器补偿电源电压的任何变化，迫使负载元件上的恒定电压降，从而保持恒定的负载。还可以包括其他电路，例如预充电电路，钳位电路，缓冲电路，微调电路，以及感测体效应的读出放大器电路。片上系统集成系统方面可以包括微控制器，混合IP和闪存系统，其具有彼此接口和互操作以进行负载补偿的功能和块。

55. 发明授权

US08049535B2 Sense amplifier for low voltage high speed sensing 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US08049535B2
公开(公告)日：2011-11-01
申请号：US12972974
申请日：2010-12-20
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G01R19/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

56. 发明授权

US07990773B2 Sub volt flash memory system 有权
标题翻译：亚伏闪存系统
公开(公告)号：US07990773B2
公开(公告)日：2011-08-02
申请号：US12623306
申请日：2009-11-20
申请人： Hieu Van Tran , Sang T. Nguyen , Anh Ly , Hung Q. Nguyen
发明人： Hieu Van Tran , Sang T. Nguyen , Anh Ly , Hung Q. Nguyen
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G11C16/08 , G11C16/30
摘要： Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.
摘要翻译：各种电路包括具有用于接收不同于电源电压和接地的体电压的体电压端子的MOS晶体管。可以选择性地设置体电压，使得一些MOS晶体管具有设置为电源电压或地的体电压，并且其它MOS晶体管具有不同的体电压。体电压可以被设置为MOS晶体管中的正向或反向偏置pn结。各种电路包括比较器，运算放大器，感测电路，解码电路和其它电路。电路可以包括在存储器系统中。

57. 发明申请

US20110122693A1 FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL 有权
标题翻译：闪存存储器阵列系统，包括顶盖存储器单元
公开(公告)号：US20110122693A1
公开(公告)日：2011-05-26
申请号：US12962343
申请日：2010-12-07
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/04 , G11C16/10 , G11C16/08
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

58. 发明申请

US20110110170A1 Non-volatile memory systems and methods including page read and/or configuration features 有权
标题翻译：非易失性存储器系统和方法，包括页面读取和/或配置特征
公开(公告)号：US20110110170A1
公开(公告)日：2011-05-12
申请号：US12961458
申请日：2010-12-06
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

59. 发明申请

US20110058425A1 Integrated Flash Memory Systems And Methods For Load Compensation 有权
标题翻译：集成闪存系统和负载补偿方法
公开(公告)号：US20110058425A1
公开(公告)日：2011-03-10
申请号：US12947719
申请日：2010-11-16
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/26
摘要： Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation.
摘要翻译：公开了系统和方法，其包括补偿存储器阵列中使用的电源电压的幅度变化的特征。根据一些方面，补偿电路可以为数据列提供可调谐的限流负载，其中可以调整负载来动态补偿电源电压的变化。在某些方面，补偿电路可以采用配置为电压跟随器的运算放大器。电压跟随器补偿电源电压的任何变化，迫使负载元件上的恒定电压降，从而保持恒定的负载。还可以包括其他电路，例如预充电电路，钳位电路，缓冲电路，微调电路，以及感测体效应的读出放大器电路。片上系统集成系统方面可以包括微控制器，混合IP和闪存系统，其具有彼此接口和互操作以进行负载补偿的功能和块。

60. 发明授权

US07839682B2 Array and pitch of non-volatile memory cells 有权
标题翻译：非易失性存储单元的阵列和间距
公开(公告)号：US07839682B2
公开(公告)日：2010-11-23
申请号：US12362106
申请日：2009-01-29
申请人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
发明人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G11C16/0408
摘要： An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array. A second high voltage line, different from the first high voltage line, is connected to the second decoder and to only the second terminal of the memory cells in the same row in the second sub array. A low voltage line is connected to the first decoder and to the thirds terminal of the memory cells in the same row of the first and second sub arrays.
摘要翻译：一组非易失性存储单元被布置成多个行和列，其中每个存储单元具有至少三个端子：用于从存储单元读出信号的第一端子，高电压的第二端子在一定操作期间提供，并且在所有操作中提供低电压的第三端子。同一列中的单元具有连接到同一列中的存储器单元的第一端的公共位线。阵列包括在同一行中彼此相邻布置的存储单元的第一和第二子阵列。第一解码器位于与第一子阵列相同的行中的第一子阵列的一侧。第二解码器被定位在与第二子阵列相同的行中的第二子阵列的另一侧。第一高压线路连接到第二解码器，并且仅连接到第一子阵列中的同一行中的存储器单元的第二端子。与第一高压线不同的第二高压线路连接到第二解码器，并且仅连接到第二子阵列中同一行中的存储器单元的第二端子。低电压线连接到第一解码器和第一和第二子阵列的同一行中的存储器单元的第三端子。

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