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    • 51. 发明申请
    • Encryption communication system
    • 加密通信系统
    • US20070160200A1
    • 2007-07-12
    • US10585997
    • 2005-01-12
    • Yuichi IshikawaNorihito FujitaAkio IijimaAtsushi Iwata
    • Yuichi IshikawaNorihito FujitaAkio IijimaAtsushi Iwata
    • H04L9/30
    • H04L63/0428H04L61/1511H04L61/6013H04L63/164
    • If the communication partner of a client node (A1a) is an encryption communication target node (C1), a DNS Proxy unit (A12a) in the client node rewrites a response to a name resolution request for the communication partner node of an application from the actual IP address of the communication partner node to a loopback address that changes depending on the communication partner. On the basis of the destination loopback address of a data packet transmitted from the application, a communication encryption module (A13a) in the client node identifies the communication partner and the encryption communication path to be used for communication with the communication partner. Hence, encryption communication can simultaneously be executed directly with a plurality of communication partner nodes by using the communication encryption module that operates as an independent process.
    • 如果客户端节点(A1a)的通信伙伴是加密通信目标节点(C1),则客户机节点中的DNS代理单元(A12a)重写对通信伙伴节点的名称解析请求的响应 从通信伙伴节点的实际IP地址到根据通信伙伴而改变的环回地址的应用。 基于从应用发送的数据分组的目的地环回地址,客户端节点中的通信加密模块(A13a)识别通信伙伴和用于与通信伙伴进行通信的加密通信路径。 因此,通过使用作为独立进程操作的通信加密模块,可以与多个通信伙伴节点直接同时执行加密通信。
    • 55. 发明授权
    • Neural network circuit
    • 神经网络电路
    • US5353383A
    • 1994-10-04
    • US909993
    • 1992-07-07
    • Kuniharu UchimuraOsamu SaitoYoshihito AmemiyaAtsushi Iwata
    • Kuniharu UchimuraOsamu SaitoYoshihito AmemiyaAtsushi Iwata
    • G06N3/063G06F15/18
    • G06K9/6287G06N3/063
    • A neural network circuit including a number n of weight coefficients (W1-Wn) corresponding to a number n of inputs, subtraction circuits for determining the difference between inputs and the weight coefficients in each input terminal, the result thereof being inputted into absolute value circuits, all calculation results of the absolute value circuits corresponding to the inputs and the weight coefficients being inputted into an addition circuit and accumulated, and this accumulation result determining the output value. A threshold value circuit determines the final output value, according to a step function pattern, a polygonal line pattern, or a sigmoid function pattern, depending on the object. In the case in which a neural network circuit is realized by means of digital circuits, the absolute value circuits can include simply EX-OR logic (exclusive OR) gates. Furthermore, in the case in which the input terminals have two input paths and two weight coefficients corresponding to each input path, the neuron circuits form a recognition area having a flexible shape which is controlled by the weight coefficients.
    • 包含对应于n个输入的权重系数(W1-Wn)数量n的神经网络电路,用于确定输入端之间的差异和每个输入端子的权重系数的减法电路,其结果被输入到绝对值电路 将与输入对应的绝对值电路和加权系数的所有计算结果输入加法电路并累加,并且该累加结果确定输出值。 根据对象,阈值电路根据阶梯函数图案,折线图案或S形函数图案确定最终输出值。 在通过数字电路实现神经网络电路的情况下,绝对值电路可以包括简单的EX-OR逻辑(异或)门。 此外,在输入端子具有两个输入路径和对应于每个输入路径的两个权重系数的情况下,神经元电路形成具有由权重系数控制的柔性形状的识别区域。
    • 56. 发明授权
    • Phase-locked loop using integrated switched filter
    • 使用集成开关滤波器的锁相环
    • US4524333A
    • 1985-06-18
    • US407150
    • 1982-08-11
    • Atsushi IwataTakao KanekoAkihiko ItoTadahiro SaitoHirokazu Fukui
    • Atsushi IwataTakao KanekoAkihiko ItoTadahiro SaitoHirokazu Fukui
    • H03L7/093H03L7/089H03L7/08
    • H03L7/0895
    • A phase-locked loop circuit provides a phase comparator which receives input signals through a first input terminal, a loop filter which receives a first output and a second output of the phase comparator, and a voltage-controlled oscillator which produces output signals of an oscillation frequency proportional to the first output and the second output of the loop filter. The signals corresponding to the output signals produced by the voltage-controlled oscillator are supplied to a second input terminal of the phase comparator so that the phase of the signals supplied to the first input terminal of the phase comparator is compared with the phase of the signals supplied to the second input terminal. In the present invention, the loop filter comprises a first capacitor connected to the output terminal of the loop filter, second and third capacitors, each having a terminal connected to the output terminal of the loop filter, and a charging circuit for electrically charging the first, second, and third capacitors. The charging circuit is connected in parallel with the second capacitor. A discharging circuit for discharging the first, second, and third capacitors is connected in parallel with the third capacitor.
    • 锁相环电路提供相位比较器,它通过第一输入端接收输入信号,接收相位比较器的第一输出和第二输出的环路滤波器和产生振荡的输出信号的压控振荡器 频率与环路滤波器的第一输出和第二输出成比例。 对应于由压控振荡器产生的输出信号的信号被提供给相位比较器的第二输入端,使得提供给相位比较器的第一输入端的信号的相位与信号的相位相比较 提供给第二输入端。 在本发明中,环路滤波器包括连接到环路滤波器的输出端子的第一电容器,第二和第三电容器,每个电容器具有连接到环路滤波器的输出端子的端子,以及充电电路,用于对第一 ,第二和第三电容器。 充电电路与第二电容器并联连接。 用于对第一,第二和第三电容器进行放电的放电电路与第三电容器并联连接。
    • 58. 发明授权
    • Switched-capacitor filter
    • 开关电容滤波器
    • US4333064A
    • 1982-06-01
    • US152558
    • 1980-05-23
    • Seiji KatoNorio UenoMitsuo KakuishiAkihiko ItoAtsushi Iwata
    • Seiji KatoNorio UenoMitsuo KakuishiAkihiko ItoAtsushi Iwata
    • H03H19/00
    • H03H19/004
    • A switched-capacitor filter provided with, at its input stage, a prefilter comprised only of a plurality of additional switched capacitors together with a switched capacitor common to the switched-capacitor filter. The switched capacitor common to the switched-capacitor filter is driven by primary clock pulses having a period T, while the additional switched capacitors are sequentially driven by secondary clock pulse groups. Each of the secondary clock pulse groups has the same period T, and the phases of the second clock pulse groups are shifted by T/2.sup.k, 2T/2.sup.k, 3T/2.sup.k . . . (2.sup.k -1)T/2.sup.k with respect to the first clock pulses (k is a positive integer). The sampled and held signals in the switched capacitors are supplied synchronously to the switched-capacitor filter.
    • 一种开关电容滤波器,在其输入级设有仅由多个附加开关电容器组成的预滤波器,以及开关电容滤波器公共的开关电容器。 开关电容滤波器公共的开关电容器由具有周期T的主时钟脉冲驱动,而附加开关电容器由次级时钟脉冲组依次驱动。 每个次级时钟脉冲组具有相同的周期T,并且第二时钟脉冲组的相位移位T / 2k,2T / 2k,3T / 2k。 。 。 (2k-1)T / 2k相对于第一时钟脉冲(k为正整数)。 开关电容器中的采样保持信号与开关电容滤波器同步地提供。