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51. 发明授权

US08232851B2 On-chip millimeter wave lange coupler 有权
标题翻译：片上毫米波兰光耦合器
公开(公告)号：US08232851B2
公开(公告)日：2012-07-31
申请号：US12404535
申请日：2009-03-16
申请人： Hanyi Ding , Kwan Him Lam
发明人： Hanyi Ding , Kwan Him Lam
IPC分类号： H01P5/18
CPC分类号： H03F3/68 , H01P5/186 , H03D3/007 , H03F3/602
摘要： A Lange coupler having a first plurality of lines on a first level and a second plurality of lines on a second level. At least one line on the first level is cross-coupled to a respective line on the second level via electromagnetic waves traveling through the first and second plurality of lines. The first and second plurality of lines may be made of metal, and the first level may be higher than the second level. A substrate may be provided into which the first and second plurality of lines are etched so as to define an on-chip Lange coupler.
摘要翻译： Lange耦合器，其具有在第一电平上的第一多个线，而在第二电平上具有第二多个线。在第一级上的至少一条线通过在第一和第二条线上行进的电磁波交叉耦合到第二电平上的相应线。第一和第二多个线可以由金属制成，并且第一电平可以高于第二电平。可以提供衬底，其中蚀刻第一和第二多条线以便限定片上朗格耦合器。

52. 发明授权

US08232173B2 Structure and design structure for high-Q value inductor and method of manufacturing the same 有权
标题翻译：高Q值电感器的结构和设计结构及其制造方法
公开(公告)号：US08232173B2
公开(公告)日：2012-07-31
申请号：US12917029
申请日：2010-11-01
申请人： Hanyi Ding , Mete Erturk , Robert A. Groves , Zhong-Xiang He , Peter J. Lindgren , Anthony K. Stamper
发明人： Hanyi Ding , Mete Erturk , Robert A. Groves , Zhong-Xiang He , Peter J. Lindgren , Anthony K. Stamper
IPC分类号： H01L21/20
CPC分类号： H01L28/10 , H01L21/76898 , H01L23/5227 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.
摘要翻译：具有高Q值电感器的结构，高Q值电感器的设计结构和制造这种结构的方法在本文中公开。还提供了一种用于产生电感器的功能设计模型的计算机辅助设计系统中的方法。该方法包括：产生同时形成在衬底中的多个垂直开口的功能性表示，其中多个垂直开口中的第一个用作通过硅通孔，并且被蚀刻比用于多个垂直开口的多个垂直开口中的第二个高Q电感; 产生形成在所述多个垂直开口中的电介质层的功能性表示; 以及生成沉积在所述多个垂直方向上的所述电介质层上的金属层的功能表示。

53. 发明授权

US08138876B2 On-chip integrated voltage-controlled variable inductor, methods of making and tuning such variable inductors, and design structures integrating such variable inductors 有权
标题翻译：片上集成电压可变电感器，制造和调谐这种可变电感器的方法，以及集成这种可变电感器的设计结构
公开(公告)号：US08138876B2
公开(公告)日：2012-03-20
申请号：US12021339
申请日：2008-01-29
申请人： Hanyi Ding , Essam F. Mina , Wayne H. Woods
发明人： Hanyi Ding , Essam F. Mina , Wayne H. Woods
IPC分类号： H01F5/00 , H01F27/28 , H01F7/06 , H01L27/08 , H03H7/00
CPC分类号： H01F21/005 , H01F17/0006 , H01F21/12 , Y10T29/4902
摘要： On-chip integrated variable inductors, methods of making and tuning an on-chip integrated variable inductor, and design structures embodying a circuit containing the on-chip integrated variable inductor. The inductor generally includes a signal line configured to carry an electrical signal, a ground line positioned in proximity to the signal line, and at least one control unit electrically coupled with the ground line. The at least one control unit is configured to open and close switch a current path connecting the ground line with a ground potential so as to change an inductance of the signal line.
摘要翻译：片上集成可变电感器，制造和调谐片上集成可变电感器的方法，以及体现包含片上集成可变电感器的电路的设计结构。电感器通常包括配置为承载电信号的信号线，位于信号线附近的接地线以及与接地线电耦合的至少一个控制单元。至少一个控制单元被配置为打开和闭合将接地线连接到地电位的电流路径，以便改变信号线的电感。

54. 发明授权

US08120145B2 Structure for a through-silicon-via on-chip passive MMW bandpass filter 有权
标题翻译：用于硅通孔片上无源MMW带通滤波器的结构
公开(公告)号：US08120145B2
公开(公告)日：2012-02-21
申请号：US12140364
申请日：2008-06-17
申请人： Amit Bavisi , Hanyi Ding , Guoan Wang , Wayne H. Woods, Jr. , Jiansheng Xu
发明人： Amit Bavisi , Hanyi Ding , Guoan Wang , Wayne H. Woods, Jr. , Jiansheng Xu
IPC分类号： H01L27/06
CPC分类号： H01P1/20363
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a substrate including a silicon layer. Furthermore, the design structure includes a metal layer on a bottom side of the silicon layer and a dielectric layer on a top side of the silicon layer. Additionally, the design structure includes a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer and a plurality of contacts in the dielectric layer in contact with the top-side interconnect. Further, the design structure includes a plurality of through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括具有硅层的基板。此外，设计结构包括在硅层的底侧上的金属层和在硅层的顶侧上的介电层。此外，该设计结构包括在电介质层的表面上的通过硅通孔带通滤波器的顶侧互连以及与顶侧互连件接触的介电层中的多个触点。此外，设计结构包括分别通过基板并与多个触点和金属层接触的多个穿硅通孔。

55. 发明申请

US20110132652A1 STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING 有权
标题翻译：基底噪声非常高的插入损耗的结构
公开(公告)号：US20110132652A1
公开(公告)日：2011-06-09
申请号：US13016126
申请日：2011-01-28
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H05K1/11 , H05K1/02
CPC分类号： H01L23/552 , H01L21/76 , H01L21/76264 , H01L23/585 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.
摘要翻译：一种结构包括具有对电噪声敏感的电路或器件的区域的衬底。此外，该结构包括延伸穿过衬底的整个厚度并围绕该区域的第一隔离结构，以及延伸穿过衬底的整个厚度并围绕该区域的第二隔离结构。

56. 发明授权

US07943404B2 Integrated millimeter wave antenna and transceiver on a substrate 有权
标题翻译：集成毫米波天线和收发器在基板上
公开(公告)号：US07943404B2
公开(公告)日：2011-05-17
申请号：US12187436
申请日：2008-08-07
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
IPC分类号： H01L21/00
CPC分类号： H01Q1/40 , H01Q9/28
摘要： A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is formed on a front side of a semiconductor substrate. At least one through substrate via provides electrical connection between the transceiver and the backside of the semiconductor substrate. The antenna, which is connected to the transceiver, is formed in a dielectric layer on the front side. The reflector plate is connected to the through substrate via, and is formed on the backside. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate trenches may be formed and filled with a dielectric material to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency.
摘要翻译：提供集成收发器，天线和接收器的半导体芯片。收发器形成在半导体衬底的前侧。至少一个通过衬底通孔提供收发器和半导体衬底的背面之间的电连接。连接到收发器的天线形成在前侧的电介质层中。反射板与穿通基板连接，并形成在背面。反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。通过衬底沟槽的阵列可以形成并填充介电材料，以减小天线和反射板之间的材料的有效介电常数，从而减小毫米波的波长并提高辐射效率。

57. 发明申请

US20100231322A1 ON-CHIP MILLIMETER WAVE LANGE COUPLER 有权
标题翻译：片上微米波浪耦合器
公开(公告)号：US20100231322A1
公开(公告)日：2010-09-16
申请号：US12404535
申请日：2009-03-16
申请人： Hanyi Ding , Kwan Him Lam
发明人： Hanyi Ding , Kwan Him Lam
IPC分类号： H01P3/08
CPC分类号： H03F3/68 , H01P5/186 , H03D3/007 , H03F3/602
摘要： A Lange coupler having a first plurality of lines on a first level and a second plurality of lines on a second level. At least one line on the first level is cross-coupled to a respective line on the second level via electromagnetic waves traveling through the first and second plurality of lines. The first and second plurality of lines may be made of metal, and the first level may be higher than the second level. A substrate may be provided into which the first and second plurality of lines are etched so as to define an on-chip Lange coupler.
摘要翻译： Lange耦合器，其具有在第一电平上的第一多个线，而在第二电平上具有第二多个线。在第一级上的至少一条线通过在第一和第二条线上行进的电磁波交叉耦合到第二电平上的相应线。第一和第二多个线可以由金属制成，并且第一电平可以高于第二电平。可以提供衬底，其中蚀刻第一和第二多条线以便限定片上朗格耦合器。

58. 发明授权

US07768762B2 Design structure for an on-chip high frequency electro-static discharge device 失效
标题翻译：片上高频静电放电装置的设计结构
公开(公告)号：US07768762B2
公开(公告)日：2010-08-03
申请号：US12144084
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H02H7/20 , H02H9/00
CPC分类号： G06F17/5068 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.
摘要翻译：描述了片上高频静电放电装置的设计结构。在一个实施例中，静电放电装置包括衬底和设置在衬底上的多个金属层。每个金属层包括多于一个电极，其中形成有多个电极，并且多个通孔与相邻金属层中的一些电极连接。所述装置还包括围绕所述金属层之一形成的间隙，其中所述间隙被气密密封，以为所述集成电路提供静电放电保护。

59. 发明授权

US07759243B2 Method for forming an on-chip high frequency electro-static discharge device 失效
标题翻译：用于形成片上高频静电放电装置的方法
公开(公告)号：US07759243B2
公开(公告)日：2010-07-20
申请号：US12144089
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： H01L21/76808 , H01L21/7682 , H01L27/0248
摘要： A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than one electrode formed therein is provided. A second dielectric layer is deposited over the capped first dielectric layer. A first hard mask dielectric layer is deposited over the second dielectric layer. A cavity trench is formed through the first hard mask dielectric layer and the second dielectric layer to the first dielectric layer, wherein the cavity trench is formed in the first dielectric layer between two adjacent electrodes. At least one via is formed through the second dielectric layer about the cavity trench. A metal trench is formed around each of the at least one via. A release opening is formed over the cavity trench. A third dielectric layer is deposited over the second dielectric layer, wherein the third dielectric layer hermetically seals the release opening to provide electro-static discharge protection.
摘要翻译：描述了在集成电路上形成片上高频静电放电装置的方法。在该方法的一个实施例中，提供了一种其上形成有多于一个电极的封盖的第一电介质层。在封盖的第一介电层上沉积第二介电层。第一硬掩模介电层沉积在第二介电层上。通过第一硬掩模电介质层和第二电介质层形成腔沟槽到第一介电层，其中在两个相邻电极之间的第一电介质层中形成空腔沟槽。至少一个通孔围绕腔沟槽形成穿过第二电介质层。在所述至少一个通孔中的每一个周围形成金属沟槽。在空腔沟槽上形成释放开口。在第二电介质层上沉积第三电介质层，其中第三介电层气密地密封释放开口以提供静电放电保护。

60. 发明授权

US07689961B2 Increased power line noise immunity in IC using capacitor structure in fill area 失效
标题翻译：在填充区域使用电容器结构增加IC中的电力线噪声抗扰度
公开(公告)号：US07689961B2
公开(公告)日：2010-03-30
申请号：US11161634
申请日：2005-08-10
申请人： Florian Braun , Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Howard S. Landis , Xuefeng Liu , Geoffrey Woodhouse
发明人： Florian Braun , Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Howard S. Landis , Xuefeng Liu , Geoffrey Woodhouse
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Increase power line noise immunity in an IC is provided by using decoupling capacitor structure in an area of the IC that is typically not used for routing, but filled with unconnected and non-functional metal squares (fills). In one embodiment, a method includes providing a circuit design layout; determining a density of a structure in an area of the circuit design layout; and in response to the density being less than a pre-determined density for the structure in the area, filling in a portion of the area with at least one capacitor structure until a combined density of the structure and the at least one capacitor structure in the area is about equal to the pre-determined density. Power line noise immunity is increased by increasing decoupling capacitance without enlarging the IC's total size by using a (fill) area that would normally be filled with unconnected and non-functional metal shapes.
摘要翻译：通过在IC的区域中使用去耦电容器结构来提供IC中的电力线噪声抗扰度，该结构通常不用于布线，而是填充有未连接和非功能金属正方形（填充）。在一个实施例中，一种方法包括提供电路设计布局; 确定电路设计布局区域中结构的密度; 并且响应于所述密度小于所述区域中的结构的预定密度，用至少一个电容器结构填充所述区域的一部分，直到所述结构和所述至少一个电容器结构的组合密度在面积约等于预定密度。通过使用通常用非连接和非功能金属形状填充的（填充）区域，通过增加去耦电容而不扩大IC的总尺寸来增加电力线噪声抗扰度。

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