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51. 发明授权

US08828840B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08828840B2
公开(公告)日：2014-09-09
申请号：US13379546
申请日：2011-04-26
申请人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
发明人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
IPC分类号： H01L21/762 , H01L21/02
CPC分类号： H01L21/76232 , H01L21/02381 , H01L21/02521 , H01L21/02639 , H01L21/02647
摘要： A semiconductor device and a method for manufacturing the same are disclosed. The method comprises: forming at least one trench in a first semiconductor layer, wherein at least lower portions of respective sidewalls of the trench tilt toward outside of the trench; filling a dielectric material in the trench, thinning the first semiconductor layer so that the first semiconductor layer is recessed with respect to the dielectric material, and epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the semiconductor layer comprise different materials from each other. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.
摘要翻译：公开了一种半导体器件及其制造方法。该方法包括：在第一半导体层中形成至少一个沟槽，其中沟槽的各个侧壁的至少下部部分朝向沟槽的外侧倾斜; 在沟槽中填充介电材料，使第一半导体层变薄，使得第一半导体层相对于电介质材料凹陷，并且在第一半导体层上外延生长第二半导体层，其中第一半导体层和半导体层包括彼此不同的材料。根据本公开的实施例，可以有效地抑制在异质外延生长期间发生的缺陷。

52. 发明授权

US08766371B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08766371B2
公开(公告)日：2014-07-01
申请号：US13256866
申请日：2011-02-25
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/70
CPC分类号： H01L29/4983 , H01L21/823807 , H01L21/823842 , H01L21/823864 , H01L29/66545 , H01L29/7845
摘要： There is provided a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention comprises: a semiconductor substrate; a channel region formed on the semiconductor substrate; a gate stack formed on the channel region; and source/drain regions formed on both sides of the channel region and embedded in the semiconductor substrate. The gate stack comprises: a gate dielectric layer formed on the channel region; and a conductive layer positioned on the gate dielectric layer. For an nMOSFET, the conductive layer has a compressive stress to apply a tensile stress to the channel region; and for a pMOSFET, the conductive layer has a tensile stress to apply a compressive stress to the channel region.
摘要翻译：提供半导体结构及其制造方法。根据本发明的半导体结构包括：半导体衬底; 形成在半导体衬底上的沟道区; 形成在沟道区上的栅叠层; 以及形成在沟道区两侧并嵌入在半导体衬底中的源/漏区。栅极堆叠包括：形成在沟道区上的栅极电介质层; 以及位于栅介质层上的导电层。对于nMOSFET，导电层具有将压应力施加到沟道区的压应力; 并且对于pMOSFET，导电层具有拉伸应力以向沟道区域施加压应力。

53. 发明授权

US08754503B2 Substrate strip plate structure for semiconductor device and method for manufacturing the same 失效
标题翻译：用于半导体器件的基板带状板结构及其制造方法
公开(公告)号：US08754503B2
公开(公告)日：2014-06-17
申请号：US13355946
申请日：2012-01-23
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L27/1218
摘要： The present invention provides a strip plate structure and a method for manufacturing the same. The strip plate structure comprises a strip plate array, which comprises a plurality of strip plates arranged with spacing in a predetermined direction on a same plane, wherein each of the strip plates has a first surface and a second surface opposite to the first surface and the strip plate array is arranged on a plane parallel to the first surface of the strip plates; a plurality of strip sheets which connect neighboring ones of the strip plates; flexible material layers, which are located on at least a portion of the surfaces of the strip sheets and/or on at least a portion of the surfaces of the strip plates.
摘要翻译：本发明提供一种带状板结构及其制造方法。带状板结构包括条板阵列，其包括在同一平面上以预定方向间隔布置的多个带状板，其中每个带状板具有第一表面和与第一表面相对的第二表面，带板阵列布置在平行于带状板的第一表面的平面上; 多个带状片，其连接相邻的条板; 柔性材料层位于带状片的至少一部分表面上和/或在带状板的至少一部分表面上。

54. 发明授权

US08674449B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08674449B2
公开(公告)日：2014-03-18
申请号：US13576550
申请日：2011-11-25
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/70 , H01L27/088
CPC分类号： H01L29/785 , H01L27/0924 , H01L29/66795
摘要： A semiconductor device and a method for manufacturing the same are disclosed. In one embodiment, the semiconductor device may comprise a semiconductor layer, a fin formed by patterning the semiconductor layer, and a gate stack crossing over the fin. The fin may comprise a doped block region at the bottom portion thereof. According to the embodiment, it is possible to effectively suppress current leakage at the bottom portion of the fin by the block region.
摘要翻译：公开了一种半导体器件及其制造方法。在一个实施例中，半导体器件可以包括半导体层，通过图案化半导体层形成的鳍和跨在翅片上的栅极堆叠。鳍可以在其底部包括掺杂块区域。根据本实施方式，能够通过块区域有效地抑制翅片底部的电流泄漏。

55. 发明授权

US08598666B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08598666B2
公开(公告)日：2013-12-03
申请号：US13504935
申请日：2011-11-03
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/12
CPC分类号： H01L27/124 , H01L21/743 , H01L27/1218 , H01L29/78
摘要： The present invention relates to a semiconductor structure and a method for manufacturing the same. A semiconductor structure comprises: a semiconductor substrate; a first insulating material layer, a first conductive material layer, a second insulating material layer, a second conductive material layer and an insulating buried layer formed in sequence on the semiconductor substrate; a semiconductor layer bonded on the insulating buried layer; transistors formed on the semiconductor layer, the channel regions of the transistors each being formed in the semiconductor layer and each having a back-gate formed from the second conductive material layer; a dielectric layer covering the semiconductor layer and the transistors; isolation structures for at least electrically isolating each transistor from its adjacent transistors, the top of the isolation structures being flush with or slightly higher than the upper surface of the semiconductor layer, and the bottom of the isolation structures being in the second insulating material layer; and a conductive contact running through the dielectric layer and extending down into the first conductive material layer.
摘要翻译：半导体结构及其制造方法技术领域本发明涉及半导体结构及其制造方法。半导体结构包括：半导体衬底; 在半导体衬底上依次形成第一绝缘材料层，第一导电材料层，第二绝缘材料层，第二导电材料层和绝缘掩埋层; 接合在绝缘掩埋层上的半导体层; 形成在半导体层上的晶体管，晶体管的沟道区各自形成在半导体层中，每一个具有由第二导电材料层形成的背栅; 覆盖半导体层和晶体管的电介质层; 用于至少将每个晶体管与其相邻晶体管电隔离的隔离结构，隔离结构的顶部与半导体层的上表面齐平或略高，隔离结构的底部位于第二绝缘材料层中; 以及导电接触件，其穿过介电层并向下延伸到第一导电材料层中。

56. 发明授权

US08546910B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08546910B2
公开(公告)日：2013-10-01
申请号：US13380723
申请日：2011-08-24
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/70
CPC分类号： H01L29/66772 , H01L29/78603 , H01L29/78696
摘要： The present invention provides a semiconductor structure, which comprises a substrate, a semiconductor base, a cavity, a gate stack, sidewall spacers, source/drain regions and a contact layer; wherein, the gate stack is located on the semiconductor base, the sidewall spacers are located on sidewalls of the gate stack, the source/drain regions are embedded within the semiconductor base and located on both sides of the gate stack, the cavity is embedded within the substrate, and the semiconductor base is suspended over the cavity, the thickness in the middle portion of the semiconductor base is greater than the thicknesses at both ends of the semiconductor base in a direction along the gate length, and both ends of the semiconductor base are connected with the substrate in a direction along the gate width; the contact layer covers exposed surfaces of the source/drain regions. Accordingly, the present invention further provides a method for manufacturing a semiconductor structure, which is favorable for reducing the contact resistance at the source/drain regions, enhancing the device performance, lowering the cost and simplifying the manufacturing process.
摘要翻译：本发明提供一种半导体结构，其包括衬底，半导体基底，空腔，栅极堆叠，侧壁间隔物，源极/漏极区域和接触层; 其中，所述栅极堆叠位于所述半导体基底上，所述侧壁间隔物位于所述栅极堆叠的侧壁上，所述源极/漏极区域被嵌入所述半导体基底内并且位于所述栅极堆叠的两侧，所述腔体嵌入衬底和半导体衬底悬挂在空腔上，半导体衬底的中间部分的厚度大于沿着栅极长度方向的半导体衬底的两端的厚度，并且半导体衬底的两端沿着所述栅极宽度的方向与所述基板连接; 接触层覆盖源极/漏极区域的暴露表面。因此，本发明还提供了一种制造半导体结构的方法，其有利于降低源/漏区的接触电阻，提高器件性能，降低成本并简化制造工艺。

57. 发明授权

US08497197B2 Method for manufacturing a high-performance semiconductor structure with a replacement gate process and a stress memorization technique 有权
标题翻译：用替代栅极工艺和应力记忆技术制造高性能半导体结构的方法
公开(公告)号：US08497197B2
公开(公告)日：2013-07-30
申请号：US13061296
申请日：2010-09-26
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L21/26586 , H01L29/1083 , H01L29/51 , H01L29/66575 , H01L29/7833 , H01L29/7847
摘要： A method for manufacturing a semiconductor structure includes providing an n-type field effect transistor comprising a source region, a drain region, and a first gate; forming a tensile stress layer on the n-type field effect transistor; removing the first gate so as to form a gate opening; performing an anneal so that the source region and the drain region memorize a stress induced by the tensile stress layer; forming a second gate; removing the tensile stress layer; and forming an interlayer dielectric layer on the n-type field effect transistor. A replacement process is combined with a stress memorization technique for enhancing the stress memorization effect and increasing mobility of electrons, which in turn improves overall properties of the semiconductor structure.
摘要翻译：一种制造半导体结构的方法，包括提供包括源区，漏区和第一栅极的n型场效应晶体管; 在n型场效应晶体管上形成拉伸应力层; 移除第一门以形成门开口; 进行退火，使得源极区域和漏极区域记忆由拉伸应力层引起的应力; 形成第二个门; 去除拉应力层; 以及在n型场效应晶体管上形成层间电介质层。替代过程与用于增强应力记忆效应和增加电子迁移率的应力记忆技术相结合，这又改善了半导体结构的整体性能。

58. 发明申请

US20130161642A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130161642A1
公开(公告)日：2013-06-27
申请号：US13003873
申请日：2010-09-26
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/78 , H01L29/66 , H01L29/788
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66636 , H01L29/66795 , H01L29/66803 , H01L29/7848
摘要： The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises an SOI substrate; a semiconductor fin formed on the SOI substrate, the semiconductor fin having a first side and a second side which are opposite to each other and stand upward on a surface of the SOI substrate, and a trench which is opened at a central portion of the second side and opposite to the first side; a channel region formed in the fin and being between the first side and the trench at the second side; source and drain regions formed in the fin and sandwiching the channel region; and a gate stack formed on the SOI substrate and being adjacent to the first side of the fin, wherein the gate stack comprises a first gate dielectric extending away from the first side and being adjacent to the channel region, a first conductor layer extending away from the first side and being adjacent to the first gate dielectric, a second gate dielectric extending away from the first side and being adjacent laterally to one side of the first conductor layer, and a second conductor layer extending away from the first side and being adjacent laterally to one side of the second gate dielectric. The embodiments of the invention can be applied in manufacturing an FinFET.
摘要翻译：本申请公开了一种半导体器件及其制造方法。半导体器件包括SOI衬底; 在所述SOI衬底上形成的半导体鳍片，所述半导体鳍片具有彼此相对并在所述SOI衬底的表面上向上并且在所述第二衬底的中心部分处开口的第一侧和第二侧; 侧和第一侧相对; 形成在所述翅片中并且在所述第二侧处在所述第一侧和所述沟槽之间的沟道区域; 源极和漏极区域形成在翅片中并夹着沟道区域; 以及形成在所述SOI衬底上并且邻近所述鳍的所述第一侧的栅极堆叠，其中所述栅极堆叠包括远离所述第一侧延伸并且邻近所述沟道区延伸的第一栅极电介质，所述第一侧并且邻近所述第一栅极电介质延伸，所述第二栅极电介质延伸远离所述第一侧并且横向邻近所述第一导体层的一侧;以及第二导体层，所述第二导体层从所述第一侧延伸并且横向相邻到第二栅极电介质的一侧。本发明的实施例可以应用于制造FinFET。

59. 发明申请

US20130146977A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130146977A1
公开(公告)日：2013-06-13
申请号：US13816227
申请日：2011-12-01
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/8238 , H01L29/66795 , H01L29/7846 , H01L29/785
摘要： The present invention discloses a semiconductor structure comprising: a semiconductor base located on an insulating layer, which is located on a semiconductor substrate; source/drain regions adjacent to opposite first sides of the semiconductor base; gates, positioned on a second set of two sides of the semiconductor base and said second set of two sides are opposite to each other; an insulating plug located on the insulating layer and embedded into the semiconductor base; and an epitaxial layer located between the insulating plug and the semiconductor base wherein the epitaxial layer is SiC for an NMOS device and the epitaxial layer is SiGe for a PMOS device. The present invention further discloses a method for manufacturing a semiconductor structure. The stress at the channel region is adjusted by forming a strained epitaxial layer, thus carrier mobility is improved and the performance of the semiconductor device is improved.
摘要翻译：本发明公开了一种半导体结构，包括：位于绝缘层上的位于半导体衬底上的半导体基底; 源极/漏极区域与半导体基底的相对的第一侧相邻; 位于所述半导体基底的第二组两侧的所述第二组彼此相对; 位于所述绝缘层上且嵌入所述半导体基底中的绝缘插头; 以及位于绝缘插头和半导体基座之间的外延层，其中外延层是用于NMOS器件的SiC，外延层是用于PMOS器件的SiGe。本发明还公开了半导体结构的制造方法。通过形成应变外延层来调整沟道区的应力，从而提高载流子迁移率，提高半导体器件的性能。

60. 发明授权

US08441050B2 Fin transistor structure and method of fabricating the same 有权
标题翻译：翅片晶体管结构及其制造方法
公开(公告)号：US08441050B2
公开(公告)日：2013-05-14
申请号：US13077858
申请日：2011-03-31
申请人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
发明人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
IPC分类号： H01L29/76 , H01L27/12 , H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A fin transistor structure and a method of fabricating the same are disclosed. In one aspect the method comprises providing a bulk semiconductor substrate, patterning the semiconductor substrate to form a fin with it body directly tied to the semiconductor substrate, patterning the fin so that gaps are formed on the bottom of the fin at source/drain regions of the transistor structure to be formed. This is performed wherein a portion of the fin corresponding to the channel region of the transistor structure to be formed is directly tied to the semiconductor substrate, while other portions of the fin at the source/drain regions are separated from the surface of the semiconductor substrate by the gaps. Also, filling an insulation material into the gaps, and fabricating the transistor structure based on the semiconductor substrate with the fin formed thereon are disclosed. Thereby, it is possible to reduce the leakage current while maintaining the advantages of body-tied structures.
摘要翻译：公开了鳍式晶体管结构及其制造方法。在一个方面，该方法包括提供体半导体衬底，图案化半导体衬底以形成鳍片，其主体直接连接到半导体衬底，图案化鳍片，使得在鳍片的底部形成间隙，在源极/漏极区域要形成的晶体管结构。这样做，其中对应于要形成的晶体管结构的沟道区的鳍的一部分直接连接到半导体衬底，而源极/漏极区的鳍的其它部分与半导体衬底的表面分离由差距。此外，公开了将绝缘材料填充到间隙中，并且制造基于其上形成有翅片的半导体衬底的晶体管结构。因此，可以在保持身体结构的优点的同时减小漏电流。

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