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51. 发明授权

US07504298B2 Method for forming memory cell and device 有权
标题翻译：用于形成存储单元和器件的方法
公开(公告)号：US07504298B2
公开(公告)日：2009-03-17
申请号：US11711569
申请日：2007-02-26
申请人： H. Montgomery Manning , David H. Wells
发明人： H. Montgomery Manning , David H. Wells
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10823
摘要： A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.
摘要翻译：存储器单元，器件和系统包括具有共享数字线的存储单元，存储电容器和被配置为选择性地将存储电容器与共享数字线电耦合的多个存取晶体管。数字线与相邻的存储器单元耦合，并且多个存取晶体管选择哪个相邻存储器单元耦合到共享数字线。形成存储单元的方法包括在衬底中形成掩埋的数字线，并且在与衬底数字线紧邻的衬底中形成垂直柱。双栅晶体管形成在垂直柱上，第一端电耦合到掩埋数字线，第二端耦合到形成于其上的存储电容器。

52. 发明授权

US07439152B2 Methods of forming a plurality of capacitors 失效
公开(公告)号：US07439152B2
公开(公告)日：2008-10-21
申请号：US10929037
申请日：2004-08-27
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10814 , H01L27/10817 , H01L27/10852
摘要： The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a substrate. Individual of the capacitor electrode openings are bounded on a first pair of opposing sides by a first capacitor electrode-forming material at one elevation and on a second pair of opposing sides by a different second capacitor electrode-forming material at the one elevation. Individual capacitor electrodes are formed within individual of the capacitor electrode openings. The capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.

53. 发明授权

US07420238B2 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US07420238B2
公开(公告)日：2008-09-02
申请号：US11188050
申请日：2005-07-22
申请人： H. Montgomery Manning , Thomas M. Graettinger , Marsela Pontoh
发明人： H. Montgomery Manning , Thomas M. Graettinger , Marsela Pontoh
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10817 , H01L27/10852 , H01L27/10894 , H01L29/66181
摘要： The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.
摘要翻译：本发明包括半导体结构，并且还包括形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电储存节点材料以形成导电容器。形成与至少一些容器物理接触的保持结构格子，随后去除绝缘材料以露出容器的外表面。保持结构可以减轻容器结构的结构完整性的倒塌或其它损失。导电容器对应于第一电容器电极。在容器的外侧壁暴露之后，电介质材料形成在容器内并沿外露的外侧壁。随后，在电介质材料上形成第二电容器电极。第一和第二电容器电极与电介质材料一起形成多个电容器器件。

54. 发明授权

US07310257B2 Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells 有权
标题翻译：具有多位或低电容存储单元的存储器件的本地数字线结构和方法
公开(公告)号：US07310257B2
公开(公告)日：2007-12-18
申请号：US11271024
申请日：2005-11-10
申请人： H. Montgomery Manning , Howard Kirsch
发明人： H. Montgomery Manning , Howard Kirsch
IPC分类号： G11C5/06 , G11C8/00
CPC分类号： G11C11/565 , G11C7/12 , G11C7/18 , G11C11/4094 , G11C11/4097
摘要： A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit lines is substantially shorter than the length of the global digit lines. As a result, the local digit lines have substantially less capacitance so that a voltage stored by a memory cell capacitor can be more easily transferred to the local digit line. The coupling circuits provide current amplification so that the voltage on the local digit lines can be more easily transferred to the global digit lines. A write back circuit is coupled to the local digit line to restore the voltage of the memory cell capacitor.
摘要翻译： DRAM阵列包括用于每列的耦合到读出放大器的一对互补数字线。每个全局数字线通过相应的耦合电路选择性地耦合到多个本地数字线。局部数字线的长度明显短于全局数字线的长度。结果，本地数字线具有实质上更小的电容，使得由存储单元电容器存储的电压可以更容易地传送到本地数字线。耦合电路提供电流放大，使得局部数字线上的电压可以更容易地传输到全局数字线。写回电路耦合到本地数字线以恢复存储单元电容器的电压。

55. 发明授权

US07199005B2 Methods of forming pluralities of capacitors 有权
公开(公告)号：US07199005B2
公开(公告)日：2007-04-03
申请号：US11196593
申请日：2005-08-02
申请人： Gurtej S. Sandhu , H. Montgomery Manning , Stephen J. Kramer
发明人： Gurtej S. Sandhu , H. Montgomery Manning , Stephen J. Kramer
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： The invention comprises methods of forming pluralities of capacitors. In one implementation, metal is formed over individual capacitor storage node locations on a substrate. A patterned masking layer is formed over the metal. The patterned masking layer comprises openings therethrough to an outer surface of the metal. Individual of the openings are received over individual of the capacitor storage node locations. A pit is formed in the metal outer surface within individual of the openings. After forming the pits, the metal is anodically oxidized through the openings effective to form a single metal oxide-lined channel in individual of the openings over the individual capacitor storage nodes. Individual capacitor electrodes are formed within the channels in electrical connection with the individual capacitor storage node locations. At least some of the metal oxide is removed from the substrate, and the individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.

56. 发明授权

US07094636B2 Method of forming a conductive line 有权
标题翻译：形成导线的方法
公开(公告)号：US07094636B2
公开(公告)日：2006-08-22
申请号：US10986415
申请日：2004-11-10
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L21/338
CPC分类号： H01L21/76897 , H01L21/76801 , H01L21/76829 , H01L21/76831 , H01L21/76895 , H01L23/485 , H01L2924/0002 , Y10S257/90 , H01L2924/00
摘要： A method of forming a conductive line includes forming conductive material received over a semiconductor substrate into a line having opposing sidewalls. Insulative material is deposited over the line, and is planarized. An insulating spacer forming layer is deposited over the line and the planarized insulative material. The spacer forming layer is anisotropically etched form a pair of insulative spacers over the opposing line sidewalls with the insulative material being received between at least one of the sidewalls and one insulative spacer formed thereover. The insulative material as so received has a maximum lateral thickness which is greater than a maximum lateral thickness of the one sidewall spacer.
摘要翻译：形成导线的方法包括将接收在半导体衬底上的导电材料形成具有相对侧壁的线。绝缘材料沉积在线上，并被平坦化。绝缘间隔物形成层沉积在线上和平坦化的绝缘材料上。间隔物形成层在相对的线侧壁上各向异性地蚀刻成一对绝缘隔离物，绝缘材料被容纳在至少一个侧壁和一个形成在其上的一个绝缘间隔物之间。如此接收的绝缘材料具有大于侧壁间隔件的最大横向厚度的最大横向厚度。

57. 发明授权

US06984549B1 Methods of forming semiconductor fuse arrangements 失效
标题翻译：形成半导体保险丝装置的方法
公开(公告)号：US06984549B1
公开(公告)日：2006-01-10
申请号：US10922492
申请日：2004-08-19
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , Y10S257/91 , H01L2924/00
摘要： The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region relative to the other links, and the region where a link makes contact to the electrically conductive plate is a fuse. The invention also includes methods of forming semiconductor fuse arrangements.
摘要翻译：本发明包括在多个导电连接件上并与之电接触的包含导电板的半导体熔丝装置。每个链接件相对于其它连接件与导电板接触作为一个单独的区域，并且链接件与导电板接触的区域是熔丝。本发明还包括形成半导体熔丝装置的方法。

58. 发明授权

US06982203B2 Method of fabricating integrated circuitry 失效
标题翻译：集成电路的制造方法
公开(公告)号：US06982203B2
公开(公告)日：2006-01-03
申请号：US10729260
申请日：2003-12-05
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L21/76801 , H01L21/76829 , H01L21/76831 , H01L21/76895 , H01L23/485 , H01L2924/0002 , Y10S257/90 , H01L2924/00
摘要： A method of fabricating integrated circuitry includes forming a conductive line having opposing sidewalls over a semiconductor substrate, and having an outer etch stop cap. An insulating layer is deposited over the substrate and the line. The insulating layer is planarize polished using the outer etch stop cap as an etch stop. After the planarize polishing, the insulating layer is etched proximate the line alonge at least a portion of at least one sidewall of the line. After the etching, an insulating spacer forming layer is deposited over the substrate and the line, and it is anisotropically etched to form an insulating sidewall spacer along said portion of the at least one sidewall.
摘要翻译：制造集成电路的方法包括在半导体衬底上形成具有相对侧壁的导电线，并且具有外蚀刻停止帽。绝缘层沉积在衬底和线上。使用外部蚀刻停止帽作为蚀刻停止层，使绝缘层平坦化。在平坦化抛光之后，绝缘层在该线的至少一个侧壁的至少一部分上靠近线路蚀刻。在蚀刻之后，将绝缘间隔物形成层沉积在衬底和线上，并且各向异性蚀刻以沿着至少一个侧壁的所述部分形成绝缘侧壁间隔物。

59. 发明授权

US06384454B2 Process for manufacturing integrated circuit SRAM 失效
标题翻译：集成电路SRAM的制造工艺
公开(公告)号：US06384454B2
公开(公告)日：2002-05-07
申请号：US09757844
申请日：2001-01-10
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L31113
CPC分类号： H01L27/11 , H01L27/1108
摘要： An SRAM cell is described which has a reduced cell area, and a reduced processing cost from conventional SRAM's. A fabrication process is described where self-aligned contacts to substrate active area and contact to a first layer of polysilicon are formed in one etch step. Electrical connection between the substrate and polysilicon is provided through a conductive layer coupled to the contacts. Self aligned contacts are fabricated to contact the active area.
摘要翻译：描述了具有减小的单元面积的SRAM单元，并且降低了来自常规SRAM的处理成本。描述制造工艺，其中在一个蚀刻步骤中形成与衬底有源区域的自对准接触和与第一多晶硅层的接触。通过耦合到触点的导电层提供衬底和多晶硅之间的电连接。制造自对准的触点以接触有源区域。

60. 发明授权

US6163044A Method and circuit for lowering standby current in an integrated circuit 失效
公开(公告)号：US6163044A
公开(公告)日：2000-12-19
申请号：US027111
申请日：1998-02-18
申请人： H. Montgomery Manning
发明人： H. Montgomery Manning
IPC分类号： H01L27/02 , H01L29/02
CPC分类号： H01L27/0214
摘要： An integrated circuit includes a substrate pump circuit developing an internal back-bias voltage on an output, and an external terminal adapted to receive an external back-bias voltage. A semiconductor substrate is coupled to the external terminal and to the output of the substrate pump circuit. The semiconductor substrate includes at least one transistor formed in the semiconductor substrate which has a first threshold voltage when the internal back-bias voltage is applied to the substrate. The at least one transistor has a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal.

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