专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US5485490A Method and circuitry for clock synchronization 失效
标题翻译：时钟同步的方法和电路
公开(公告)号：US5485490A
公开(公告)日：1996-01-16
申请号：US346363
申请日：1994-11-29
申请人： Wingyu Leung , Mark A. Horowitz
发明人： Wingyu Leung , Mark A. Horowitz
IPC分类号： H03K3/0231 , H03K3/03 , H03K3/354 , H03L7/06 , H03L7/07 , H03L7/099 , H04J3/06 , H04L7/033 , H04C7/00
CPC分类号： H03L7/0996 , H03K3/0231 , H03K3/0322 , H03K3/354 , H03L7/06 , H03L7/07 , H04L7/0337
摘要： Circuitry for performing fine phase adjustment within a phase locked loop is described. The phase selector selects an even phase signal and an odd phase signal from the twelve phase signals output by the VCO. The even and odd phase signals are selected by an even select signal and an odd select signal, respectively. The phase interpolator interpolates between the even phase signal and the odd phase signal to generate an output signal. The affect of the even phase signal and the odd phase signal on the output signal is determined by an even weighting signal and an odd weighting signal, respectively. The weighting signals prevent glitches from appearing on the output signal when either the even phase signal or the odd phase signal is switching. A method of performing fine phase adjustment in a phase locked loop is also described.
摘要翻译：描述用于在锁相环内进行精细相位调整的电路。相位选择器从VCO输出的十二相信号中选择偶相信号和奇相位信号。偶数和奇数相位信号分别由偶数选择信号和奇数选择信号选择。相位插值器在偶相信号和奇相位信号之间内插，以产生输出信号。偶数相位信号和奇数相位信号对输出信号的影响分别由均匀加权信号和奇数加权信号决定。当偶数相位信号或奇数相位信号正在切换时，加权信号防止在输出信号上出现毛刺。还描述了在锁相环中执行精细相位调整的方法。

52. 发明授权

US5254883A Electrical current source circuitry for a bus 失效
标题翻译：总线电流源电路
公开(公告)号：US5254883A
公开(公告)日：1993-10-19
申请号：US872919
申请日：1992-04-22
申请人： Mark A. Horowitz , James A. Gasbarro , Wingyu Leung
发明人： Mark A. Horowitz , James A. Gasbarro , Wingyu Leung
IPC分类号： G06F3/00 , G05F1/613 , G11C11/401 , H03K19/0175 , H03K19/0185 , H04L25/02 , H03K19/003
CPC分类号： H04L25/0282 , H03K19/018585 , H04L25/0298
摘要： Electrical current source circuitry for a bus is described. The circuitry includes transistor circuitry coupled between the bus and ground for controlling bus current, control circuitry coupled to the transistor circuitry, and a controller coupled to the control circuitry for controlling the transistor circuitry. The controller comprises a variable level circuit comprising setting circuitry for setting a desired current for the bus and transistor reference circuitry coupled to the setting circuitry. The variable level circuit provides a first voltage. Voltage reference circuitry provides a reference voltage. Comparison circuitry is coupled to the voltage reference circuitry and to the variable level circuit for comparing the first voltage with the reference voltage. Logic circuitry is responsive to a trigger signal from the comparison circuitry. An output of the logic circuitry is coupled to the control circuitry in order to turn on the transistor circuitry in a manner dependent upon an output of the logic circuitry.
摘要翻译：描述了用于总线的电流源电路。电路包括耦合在总线和地之间的晶体管电路，用于控制总线电流，耦合到晶体管电路的控制电路以及耦合到控制电路的用于控制晶体管电路的控制器。控制器包括可变电平电路，其包括用于设置用于总线的期望电流的设置电路和耦合到该设置电路的晶体管参考电路。可变电平电路提供第一电压。电压参考电路提供参考电压。比较电路耦合到电压参考电路和可变电平电路，用于将第一电压与参考电压进行比较。逻辑电路响应来自比较电路的触发信号。逻辑电路的输出耦合到控制电路，以便以取决于逻辑电路的输出的方式接通晶体管电路。

53. 发明授权

US5008568A CMOS output driver 失效
标题翻译： CMOS输出驱动
公开(公告)号：US5008568A
公开(公告)日：1991-04-16
申请号：US565169
申请日：1990-08-08
申请人： Wingyu Leung , Chuen-Der Lien
发明人： Wingyu Leung , Chuen-Der Lien
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/0185 , H03K19/00361
摘要： A transistor configured as a capacitor is connected between the gate and drain of an output, pull-down transistor to limit the rate of change (di/dt) of the current conducted through the pull-down transistor during the turn-on of the transistor to limit ground bounce (transients). Drive for the pull-down transistor is provided, in part, by a NOR gate, the transistors of which are sized to provide a finite resistive to the pull-down transistor. Additional drive for the pull-down transistor is provided by a transistor connected to function as a resistive pull-up between the gate and the drain of the pull-down transistor.
摘要翻译：配置为电容器的晶体管连接在输出下拉晶体管的栅极和漏极之间，以限制晶体管导通期间通过下拉晶体管传导的电流的变化率（di / dt）限制地面反弹（瞬变）。用于下拉晶体管的驱动部分地由或非门提供，其中晶体管的尺寸被设计成提供对下拉晶体管的有限电阻。下拉晶体管的附加驱动器由连接到下拉晶体管的栅极和漏极之间的电阻上拉的晶体管提供。

54. 发明授权

US4933574A BiCMOS output driver 失效
标题翻译： BiCMOS输出驱动
公开(公告)号：US4933574A
公开(公告)日：1990-06-12
申请号：US303855
申请日：1989-01-30
申请人： Chuen-Der Lien , Wingyu Leung
发明人： Chuen-Der Lien , Wingyu Leung
IPC分类号： H03K17/16 , H03K17/687 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944
CPC分类号： H03K19/01721 , H03K19/00361 , H03K19/09448
摘要： A bipolar transistor and two field-effect transistors are connected in a BiCMOS pull-down configuration to pull-down to a (first) predetermined potential level the potential developed on an output line when a high logic level potential is developed on an input line. To maximize switching speed and to minimize ground bounce (transients), the bipolar transistor is not permitted to go into saturation. A pair of transistors, connected in an inverter configuration, develop a signal which indicates when the bipolar transistor pulls-down the level of the potential on the output line below a (second) predetermined potential level. From a signal developed from the input line signal and a signal developed from the inverter developed signal, a gate develops a signal which drives a transistor that pulls-down from the (first) predetermined potential level to a low logic level potential the output line potential three gate delay times after the output line potential level falls below the (second) predetermined potential level.

55. 发明授权

US07684229B2 Scalable embedded DRAM array 有权
标题翻译：可扩展嵌入式DRAM阵列
公开(公告)号：US07684229B2
公开(公告)日：2010-03-23
申请号：US12048176
申请日：2008-03-13
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G11C11/24 , G11C5/14 , H01L21/8244
CPC分类号： G11C8/08 , G11C11/4085 , G11C2207/104 , H01L27/10897
摘要： A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor layout area is reduced by the square of the scale factor, while cell capacitance is reduced by the scale factor. The voltage used to supply the logic transistors is scaled down from the first process to the second process. However, the voltage used to supply the sense amplifiers remains constant in both processes. Thus, in an embedded DRAM array of the second process, sense amplifiers are supplied by a greater voltage than the logic transistors. This allows the sensing voltage of DRAM cells to be maintained from one process generation to another, while allowing memory size to scale with the square of the process scale factor.
摘要翻译：一种用于将嵌入式DRAM阵列从第一过程缩放到第二过程的方法和装置，其中缩放涉及通过恒定比例因子来减小特征的线性尺寸。从第一个处理过程到第二个处理过程，DRAM单元电容器布局面积减小了比例因子的平方，而单元电容则由缩放因子减小。用于提供逻辑晶体管的电压从第一过程缩减到第二过程。然而，用于提供感测放大器的电压在两个过程中保持不变。因此，在第二工艺的嵌入式DRAM阵列中，读出放大器由比逻辑晶体管更大的电压提供。这允许将DRAM单元的感测电压从一个处理世代维持到另一个，同时允许存储器大小与过程比例因子的平方成比例。

56. 发明申请

US20080159036A1 Scalable Embedded DRAM Array 有权
公开(公告)号：US20080159036A1
公开(公告)日：2008-07-03
申请号：US12048170
申请日：2008-03-13
申请人： Wingyu Leung
发明人： Wingyu Leung
IPC分类号： G11C7/02
CPC分类号： G11C8/08 , G11C11/4085 , G11C2207/104 , H01L27/10897
摘要： A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor layout area is reduced by the square of the scale factor, while cell capacitance is reduced by the scale factor. The voltage used to supply the logic transistors is scaled down from the first process to the second process. However, the voltage used to supply the sense amplifiers remains constant in both processes. Thus, in an embedded DRAM array of the second process, sense amplifiers are supplied by a greater voltage than the logic transistors. This allows the sensing voltage of DRAM cells to be maintained from one process generation to another, while allowing memory size to scale with the square of the process scale factor.

57. 发明授权

US07392456B2 Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory 有权
标题翻译：在半导体存储器中促进高速字节写入的预测性纠错码产生
公开(公告)号：US07392456B2
公开(公告)日：2008-06-24
申请号：US10997604
申请日：2004-11-23
申请人： Wingyu Leung , Kit Sang Tam
发明人： Wingyu Leung , Kit Sang Tam
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1056 , G11C11/4078
摘要： Write check bits are generated in a predictive manner for partial-word write transactions in a memory system implementing error code correction. A read data word and associated read check bits are read from an address of the memory. If an error exists in a byte of the read data word, this byte is identified. At the same time, one or more bytes of the uncorrected read data word are merged with one or more bytes of a write data word, thereby creating a merged data word. Write check bits are generated in response to the merged data word. If the merged data word includes a byte of the read data word, which contains an error, the write check bits are modified to reflect this error. The merged data word and the modified (or unmodified) write check bits are then written to the address of the memory.
摘要翻译：以实现错误代码校正的存储器系统中的部分字写入事务的预测方式生成写校验位。从存储器的地址读取读取数据字和相关联的读取校验位。如果读取数据字的一个字节存在错误，则识别该字节。同时，未校正的读取数据字的一个或多个字节与写入数据字的一个或多个字节合并，从而创建合并的数据字。响应于合并的数据字生成写校验位。如果合并的数据字包含包含错误的读取数据字的字节，则修改校验位以反映该错误。合并的数据字和修改的（或未修改的）写入校验位然后被写入存储器的地址。

58. 发明授权

US06714470B2 High-speed read-write circuitry for semi-conductor memory devices 有权
标题翻译：半导体存储器件的高速读写电路
公开(公告)号：US06714470B2
公开(公告)日：2004-03-30
申请号：US09963984
申请日：2001-09-25
申请人： Wingyu Leung , Jui-Pin Tang
发明人： Wingyu Leung , Jui-Pin Tang
IPC分类号： G11C700
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/22
摘要： A semi-conductor memory device having a wide write data bandwidth is provided with high speed read-write circuitry having data amplifiers that are activated to accelerate amplification of write data signals being driven by write data drivers onto data lines of the cell array of the device during memory write cycles, as well as activated to amplify read data signals on the data lines during memory read cycles. Moreover, the data amplifiers are activatedin a self-timed manner. In one embodiment, the device is further provided with a read data buffer that is constituted with a regenerative latch and an input stage, and a write data buffer having multiple entries. The input stage of the read data buffer isolates or couples the regenerative latch to the data lines depending on whether the data lines are in a pre-charged state or not. In one embodiment, the data amplifiers and the write drivers are further arranged to enable write data in the write buffer to be merged with the masked read data from the memory array when a read transaction hits the write buffer.
摘要翻译：具有宽写入数据带宽的半导体存储器件被提供有具有数据放大器的高速读写电路，该数据放大器被激活以加速由写数据驱动器驱动的写入数据信号放大到器件的单元阵列的数据线上在存储器写周期期间，以及在存储器读周期期间被激活以放大数据线上的读数据信号。此外，数据放大器以自定时的方式被激活。在一个实施例中，该设备还具有由再生锁存器和输入级构成的读取数据缓冲器和具有多个条目的写入数据缓冲器。读取数据缓冲器的输入级根据数据线是否处于预充电状态，将再生锁存器隔离或耦合到数据线。在一个实施例中，数据放大器和写入驱动器被进一步布置成使得当读取事务触发写入缓冲器时，写入缓冲器中的写入数据与来自存储器阵列的屏蔽的读取数据合并。

59. 发明授权

US06707743B2 Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division 有权
标题翻译：用于使用多个时钟分割完全隐藏DRAM设备中的刷新操作的方法和装置
公开(公告)号：US06707743B2
公开(公告)日：2004-03-16
申请号：US10114282
申请日：2002-04-03
申请人： Wingyu Leung , Jae-Kwang Sim
发明人： Wingyu Leung , Jae-Kwang Sim
IPC分类号： G11C722
CPC分类号： G11C11/005 , G11C7/22 , G11C11/406 , G11C11/40618
摘要： A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A clock division scheme is implemented to allow N external accesses and one refresh operation to be performed during N consecutive clock cycles.
摘要翻译：一种用于处理需要周期性刷新操作的DRAM阵列或其他存储器阵列的刷新的方法和装置，使得刷新不需要显式控制信号，也不需要在存储器阵列和外部存取客户端之间握手通信。该方法和装置处理外部访问和刷新操作，使得刷新操作在任何情况下不干扰外部访问。因此，可以从DRAM或1晶体管单元构建SRAM兼容器件。实现时钟分配方案，以允许在N个连续时钟周期内执行N个外部访问和一个刷新操作。

60. 发明授权

US06573548B2 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same 有权
公开(公告)号：US06573548B2
公开(公告)日：2003-06-03
申请号：US10033690
申请日：2001-11-02
申请人： Wingyu Leung , Fu-Chieh Hsu
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H01L31112
CPC分类号： H01L27/1085 , G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C2207/104 , H01L21/76895 , H01L27/0214 , H01L27/10835 , H01L27/10852 , H01L27/10873 , H01L28/86 , H01L28/91
摘要： A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式