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51. 发明授权

US09520321B2 Integrated circuits and methods for fabricating integrated circuits with self-aligned vias 有权
标题翻译：用于制造具有自对准通孔的集成电路的集成电路和方法
公开(公告)号：US09520321B2
公开(公告)日：2016-12-13
申请号：US14633914
申请日：2015-02-27
申请人： GLOBALFOUNDRIES, Inc.
发明人： Errol Todd Ryan , Sean X. Lin
IPC分类号： H01L21/44 , H01L29/40 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76805 , H01L21/76829 , H01L21/76865 , H01L21/76877 , H01L21/76897 , H01L21/823475 , H01L23/5226 , H01L23/53238 , H01L23/53295
摘要： Integrated circuits and methods for fabricating integrated circuits with self-aligned vias are disclosed. A method for fabricating an integrated circuit includes forming a first conductive interconnect line overlying a semiconductor substrate. The method forms an insulator cap defining a gap overlying the first conductive interconnect line. An upper interlayer dielectric material is deposited over the insulator cap and in the gap over the first conductive interconnect line. A via is etched through the upper interlayer dielectric material and into the gap to expose the first conductive interconnect line. The method deposits a conductive material into the via to form a conductive via in contact with the first conductive interconnect line.
摘要翻译：公开了用于制造具有自对准通孔的集成电路的集成电路和方法。一种用于制造集成电路的方法包括形成覆盖半导体衬底的第一导电互连线。该方法形成限定覆盖在第一导电互连线上的间隙的绝缘体帽。在绝缘体盖上并在第一导电互连线上的间隙中沉积上层间绝缘材料。将通孔蚀刻通过上层间介电材料并进入间隙以露出第一导电互连线。该方法将导电材料沉积到通孔中以形成与第一导电互连线接触的导电通孔。

52. 发明申请

US20160254185A1 INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SELF-ALIGNED VIAS 有权
标题翻译：集成电路与自对准VIAS整合电路的整合方法
公开(公告)号：US20160254185A1
公开(公告)日：2016-09-01
申请号：US14633914
申请日：2015-02-27
申请人： GLOBALFOUNDRIES, Inc.
发明人： Errol Todd Ryan , Sean X. Lin
IPC分类号： H01L21/768 , H01L23/532 , H01L23/528 , H01L23/522 , H01L21/311 , H01L21/02
CPC分类号： H01L21/76805 , H01L21/76829 , H01L21/76865 , H01L21/76877 , H01L21/76897 , H01L21/823475 , H01L23/5226 , H01L23/53238 , H01L23/53295
摘要： Integrated circuits and methods for fabricating integrated circuits with self-aligned vias are disclosed. A method for fabricating an integrated circuit includes forming a first conductive interconnect line overlying a semiconductor substrate. The method forms an insulator cap defining a gap overlying the first conductive interconnect line. An upper interlayer dielectric material is deposited over the insulator cap and in the gap over the first conductive interconnect line. A via is etched through the upper interlayer dielectric material and into the gap to expose the first conductive interconnect line. The method deposits a conductive material into the via to form a conductive via in contact with the first conductive interconnect line.
摘要翻译：公开了用于制造具有自对准通孔的集成电路的集成电路和方法。一种用于制造集成电路的方法包括形成覆盖半导体衬底的第一导电互连线。该方法形成限定覆盖在第一导电互连线上的间隙的绝缘体帽。在绝缘体盖上并在第一导电互连线上的间隙中沉积上层间绝缘材料。将通孔蚀刻通过上层间介电材料并进入间隙以露出第一导电互连线。该方法将导电材料沉积到通孔中以形成与第一导电互连线接触的导电通孔。

53. 发明授权

US09431294B2 Methods of producing integrated circuits with an air gap 有权
标题翻译：具有气隙的集成电路的制造方法
公开(公告)号：US09431294B2
公开(公告)日：2016-08-30
申请号：US14525796
申请日：2014-10-28
申请人： GLOBALFOUNDRIES, Inc.
发明人： Ming He , Errol Todd Ryan , Roderick Alan Augur , Craig Child , Larry Zhao
IPC分类号： H01L21/4763 , H01L21/76 , H01L21/768 , H01L21/02 , H01L23/532 , H01L23/528
CPC分类号： H01L21/7682 , H01L21/0217 , H01L21/02274 , H01L21/0228 , H01L21/76831 , H01L21/76834 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.
摘要翻译：提供了集成电路及其制造方法。一种用于制造集成电路的方法包括在电介质层中形成互连沟槽，以及形成覆盖在介电层上和互连沟槽内的共形阻挡层。通过从互连沟槽底部去除共形阻挡层而形成阻挡间隔物，并且在形成阻挡间隔物之后在互连沟槽内形成互连。在邻近阻挡间隔物的电介质层中形成气隙沟槽，并且顶盖形成在互连和气隙沟槽上方，顶盖与气隙沟槽连接，以在气隙沟槽中产生气隙。

54. 发明授权

US09349631B2 Method for defining an isolation region(s) of a semiconductor structure 有权
标题翻译：用于限定半导体结构的隔离区域的方法
公开(公告)号：US09349631B2
公开(公告)日：2016-05-24
申请号：US14504479
申请日：2014-10-02
申请人： GLOBALFOUNDRIES Inc.
发明人： Errol Todd Ryan
IPC分类号： H01L21/76 , H01L21/762 , H01L21/265 , H01L21/02
CPC分类号： H01L21/76224 , H01L21/02337 , H01L21/2236 , H01L21/26566
摘要： Methods for defining an isolation region of a semiconductor structure are provided. The method includes, for instance: providing a semiconductor structure with a recess therein; disposing an insulator layer conformally within the recess in the semiconductor structure to partially fill the recess; modifying at least one material property of the insulator layer to obtain a densified insulator layer within the recess, where the modifying reduces a thickness of the densified insulator layer compared to that of the insulator layer; and depositing at least one additional insulator layer within the recess over the densified insulator layer, where the densified insulator layer within the recess defines, at least in part, an isolation region of the semiconductor structure.
摘要翻译：提供了用于限定半导体结构的隔离区域的方法。该方法包括例如：提供其中具有凹部的半导体结构; 在半导体结构中的凹部内共形布置绝缘体层以部分地填充凹部; 修改绝缘体层的至少一种材料性质以在凹陷内获得致密化的绝缘体层，其中改性减少了与绝缘体层相比较的致密绝缘体层的厚度; 以及在所述凹陷内的所述致密绝缘体层上沉积至少一个额外的绝缘体层，其中所述凹陷内的所述致密绝缘体层至少部分地限定所述半导体结构的隔离区域。

55. 发明授权

US09224639B2 Method to etch cu/Ta/TaN selectively using dilute aqueous Hf/hCl solution 有权
公开(公告)号：US09224639B2
公开(公告)日：2015-12-29
申请号：US14807480
申请日：2015-07-23
申请人： Intermolecular Inc. , GLOBALFOUNDRIES, Inc.
发明人： Anh Duong , Errol Todd Ryan
IPC分类号： H01L21/461 , H01L21/768 , H01L21/321 , H01L23/528 , H01L23/532
CPC分类号： H01L21/76843 , H01L21/3212 , H01L21/32134 , H01L21/76802 , H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L23/5283 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.

56. 发明授权

US09123785B1 Method to etch Cu/Ta/TaN selectively using dilute aqueous HF/HCI solution 有权
标题翻译：使用稀HF / HCl溶液选择性地蚀刻Cu / Ta / TaN的方法
公开(公告)号：US09123785B1
公开(公告)日：2015-09-01
申请号：US14202268
申请日：2014-03-10
申请人： Intermolecular Inc. , GLOBALFOUNDRIES, Inc.
发明人： Anh Duong , Errol Todd Ryan
IPC分类号： H01L21/311 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76843 , H01L21/3212 , H01L21/32134 , H01L21/76802 , H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L23/5283 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and HCl can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.
摘要翻译：可以选择性地对Ta / TaN阻挡衬垫和SiC硬掩模层进行蚀刻，例如，以减少潜在的铜污染。铜膜可以比衬垫更凹入，以进一步增强保护。可以使用包含HF和HCl的混合物的湿式蚀刻溶液来相对于衬垫材料选择性地蚀刻铜，例如，铜膜可以凹陷在2和3nm之间，并且阻挡衬里膜可以凹陷在1.5和 2 nm。

57. 发明授权

US09054052B2 Methods for integration of pore stuffing material 有权
标题翻译：孔填料的整合方法
公开(公告)号：US09054052B2
公开(公告)日：2015-06-09
申请号：US13903802
申请日：2013-05-28
申请人： GLOBALFOUNDRIES Inc.
发明人： Nicholas Vincent Licausi , Errol Todd Ryan , Ming He , Moosung M. Chae , Kunaljeet Tanwar , Larry Zhao , Christian Witt , Ailian Zhao , Sean X. Lin , Xunyuan Zhang
IPC分类号： H01L21/314 , H01L21/308 , H01L21/32 , H01L29/06
CPC分类号： H01L21/314 , H01L21/308 , H01L21/3105 , H01L21/31144 , H01L21/32 , H01L21/76814 , H01L21/7682 , H01L21/76825 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L29/06 , H01L2221/1047
摘要： A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.
摘要翻译：提供了一种在制造期间减少对超低k层的损伤的方法的方法。一方面，一种方法包括：提供含有填充有孔填充材料的孔的固化的超低k膜; 以及改变超低k膜的暴露表面以在超低k膜中提供改性层。在另一方面，提供一种在超低k膜的表面上包含改性层的半导体器件。

58. 发明申请

US20150126028A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SURFACE MODIFICATION TO SELECTIVELY INHIBIT ETCHING 有权
标题翻译：使用表面修饰来选择性地抑制蚀刻来制造集成电路的方法
公开(公告)号：US20150126028A1
公开(公告)日：2015-05-07
申请号：US14071070
申请日：2013-11-04
申请人： GLOBALFOUNDRIES, Inc
发明人： Errol Todd Ryan , Kunaljeet Tanwar , Xunyuan Zhang
IPC分类号： H01L21/768
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/31144 , H01L21/321 , H01L21/32134 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/76865 , H01L21/76883
摘要： Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first exposed surface including an elemental metal material and a second exposed surface including a barrier material. The elemental metal material has a first etch rate when exposed to a wet etchant and the barrier material has a second etch rate when exposed to the wet etchant. Further, the method includes modifying the first exposed surface to form a modified first exposed surface so as to reduce the first etch rate when exposed to the wet etchant and applying the wet etchant simultaneously to the modified first exposed surface and to the second exposed surface.
摘要翻译：在各种示例性实施例中提供了用于制造集成电路的方法。在一个实施例中，制造集成电路的方法包括提供具有包括元素金属材料的第一暴露表面和包括阻挡材料的第二暴露表面的半导体衬底。当暴露于湿蚀刻剂时，元素金属材料具有第一蚀刻速率，并且当暴露于湿蚀刻剂时，阻挡材料具有第二蚀刻速率。此外，该方法包括修改第一暴露表面以形成修饰的第一暴露表面，以便当暴露于湿蚀刻剂时降低第一蚀刻速率，并将湿蚀刻剂同时施加到修饰的第一暴露表面和第二暴露表面。

59. 发明授权

US08889549B2 Methods of forming conductive structures using a sacrificial liner layer 有权
标题翻译：使用牺牲衬垫层形成导电结构的方法
公开(公告)号：US08889549B2
公开(公告)日：2014-11-18
申请号：US13766898
申请日：2013-02-14
申请人： GLOBALFOUNDRIES Inc.
发明人： Xunyuan Zhang , Nicholas V. LiCausi , Errol Todd Ryan
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76807 , H01L2221/1063
摘要： One illustrative method disclosed herein includes performing a first etching process to define a via opening in a layer of insulating material, performing at least one process operation to form a sacrificial liner layer on the sidewalls of the via opening, performing a second etching process to define a trench in the layer of insulating material, wherein the sacrificial liner layer is exposed to the second etching process, after performing the second etching process, performing a third etching process to remove the sacrificial liner layer and, after performing the third etching process, forming a conductive structure in at least the via opening and the trench.
摘要翻译：本文公开的一种说明性方法包括执行第一蚀刻工艺以在绝缘材料层中限定通孔开口，执行至少一个工艺操作以在通孔开口的侧壁上形成牺牲衬垫层，执行第二蚀刻工艺以界定在所述绝缘材料层中的沟槽，其中所述牺牲衬垫层在进行所述第二蚀刻工艺之后暴露于所述第二蚀刻工艺，执行第三蚀刻工艺以去除所述牺牲衬垫层，并且在执行所述第三蚀刻工艺之后，形成至少在通孔开口和沟槽中的导电结构。

60. 发明授权

US08835306B2 Methods for fabricating integrated circuits having embedded electrical interconnects 有权
标题翻译：具有嵌入式电气互连的集成电路的制造方法
公开(公告)号：US08835306B2
公开(公告)日：2014-09-16
申请号：US13757504
申请日：2013-02-01
申请人： GLOBALFOUNDRIES, Inc.
发明人： Errol Todd Ryan , Kunaljeet Tanwar
IPC分类号： H01L21/768
CPC分类号： H01L21/76832 , H01L21/76834 , H01L21/7684 , H01L21/76883
摘要： A method for fabricating integrated circuits includes providing a substrate including a protecting layer over an oxide layer and etching a recess through the protecting layer and into the oxide layer. A barrier material is deposited over the substrate to form a barrier layer including a first region in the recess and a second region outside the recess. A conductive material is deposited over the barrier layer and forms an embedded electrical interconnect in the recess and an overburden region outside the recess. The overburden region of the conductive material is removed and a portion of the embedded electrical interconnect is recessed. Thereafter, the barrier layer is etched to remove the second region of the barrier layer and to recess a portion of the first region of the barrier layer. After etching the barrier layer, the protecting layer is removed from the oxide layer.
摘要翻译：一种用于制造集成电路的方法包括在氧化物层上提供包括保护层的衬底，并蚀刻通过保护层的凹陷并进入氧化物层。阻挡材料沉积在衬底上以形成包含凹部中的第一区域和凹部外部的第二区域的阻挡层。导电材料沉积在阻挡层上并在凹槽中形成嵌入的电互连，并且在凹部外部形成覆盖层。去除导电材料的覆盖层区域，并且嵌入式电互连件的一部分凹陷。此后，蚀刻阻挡层以去除阻挡层的第二区域并使阻挡层的第一区域的一部分凹陷。在蚀刻阻挡层之后，从氧化物层去除保护层。

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