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51. 发明申请

US20120178211A1 CO-PACKAGING APPROACH FOR POWER CONVERTERS BASED ON PLANAR DEVICES, STRUCTURE AND METHOD 审中-公开
标题翻译：基于平面设备的电力转换器的包装方法，结构和方法
公开(公告)号：US20120178211A1
公开(公告)日：2012-07-12
申请号：US13424421
申请日：2012-03-20
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L21/8234 , H01L21/50 , H01L21/283
CPC分类号： H01L27/088 , H01L21/26513 , H01L21/823437 , H01L21/823487 , H01L23/535 , H01L23/62 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66712 , H01L29/66734 , H01L29/7802 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7816 , H01L29/7835 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/1461 , H01L2924/30107 , H01L2924/3025 , H02M7/003 , H01L2924/00
摘要： A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a planar vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the power die.
摘要翻译：电压转换器包括具有可以形成在单个管芯（“PowerDie”）上的高侧器件和低侧器件的输出电路。高侧器件可以包括横向扩散金属氧化物半导体（LDMOS），而低侧器件可以包括平面垂直扩散金属氧化物半导体（VDMOS）。电压转换器还可以包括在不同的管芯上的控制器电路，其可以电耦合到功率管芯并且与电源管芯共同封装。

52. 发明授权

US08168490B2 Co-packaging approach for power converters based on planar devices, structure and method 失效
标题翻译：基于平面装置的电力转换器的共包装方法，结构和方法
公开(公告)号：US08168490B2
公开(公告)日：2012-05-01
申请号：US12470229
申请日：2009-05-21
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L21/8238
CPC分类号： H01L27/088 , H01L21/26513 , H01L21/823437 , H01L21/823487 , H01L23/535 , H01L23/62 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66712 , H01L29/66734 , H01L29/7802 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7816 , H01L29/7835 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/1461 , H01L2924/30107 , H01L2924/3025 , H02M7/003 , H01L2924/00
摘要： A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a planar vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the power die.
摘要翻译：电压转换器包括具有可以形成在单个管芯（“PowerDie”）上的高侧器件和低侧器件的输出电路。高侧器件可以包括横向扩散金属氧化物半导体（LDMOS），而低侧器件可以包括平面垂直扩散金属氧化物半导体（VDMOS）。电压转换器还可以包括在不同的管芯上的控制器电路，其可以电耦合到功率管芯并且与电源管芯共同封装。

53. 发明申请

US20110186959A1 DIAMOND SOI WITH THIN SILICON NITRIDE LAYER 有权
标题翻译：具有薄硅酸盐层的金刚石SOI
公开(公告)号：US20110186959A1
公开(公告)日：2011-08-04
申请号：US12887797
申请日：2010-09-22
申请人： Rick C. Jerome , Francois Hebert , Craig McLachlan , Kevin Hoopingarner
发明人： Rick C. Jerome , Francois Hebert , Craig McLachlan , Kevin Hoopingarner
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L21/02107
摘要： A method and structure for a semiconductor device, the device including a handle wafer, a diamond layer formed directly on a front side of the handle wafer, and a thick oxide layer formed directly on a back side of the handle wafer, the oxide of a thickness to counteract tensile stresses of the diamond layer. Nitride layers are formed on the outer surfaces of the diamond layer and thick oxide layer and a polysilicon is formed on outer surfaces of the nitride layers. A device wafer is bonded to the handle wafer to form the semiconductor device.
摘要翻译：一种用于半导体器件的方法和结构，所述器件包括处理晶片，直接形成在所述手柄晶片前侧上的金刚石层以及直接形成在所述手柄晶片的背面上的厚氧化物层，所述氧化物抵抗金刚石层的拉伸应力的厚度。在金刚石层和厚氧化物层的外表面上形成氮化物层，并且在氮化物层的外表面上形成多晶硅。器件晶片被结合到处理晶片以形成半导体器件。

54. 发明申请

US20110156682A1 VOLTAGE CONVERTER WITH INTEGRATED SCHOTTKY DEVICE AND SYSTEMS INCLUDING SAME 审中-公开
标题翻译：具有集成肖特基特征的电压转换器和包括它们的系统
公开(公告)号：US20110156682A1
公开(公告)日：2011-06-30
申请号：US12898664
申请日：2010-10-05
申请人： Dev Alok Girdhar , Francois Hebert
发明人： Dev Alok Girdhar , Francois Hebert
IPC分类号： H02M3/156 , H01L27/07 , H01L21/74
CPC分类号： H01L27/0629 , H01L24/29 , H01L24/32 , H01L24/48 , H01L27/088 , H01L29/0619 , H01L29/0653 , H01L29/1083 , H01L29/4175 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/66659 , H01L29/7835 , H01L29/872 , H01L2224/48247 , H01L2224/48464 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01029 , H01L2924/01078 , H01L2924/0781 , H01L2924/10253 , H01L2924/12032 , H01L2924/12036 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device such as a voltage converter includes a circuit stage such as an output stage having a high side device and a low side device which can be formed on a single die (i.e., a “PowerDie”) and connected to each other through a semiconductor substrate, and further includes a Schottky diode integrated with at least one of the low side device and the high side device. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie. Various embodiments of the Schottky diode can provide Schottky protection and, additionally JFET protection for the Schottky device.
摘要翻译：诸如电压转换器的半导体器件包括诸如具有高侧器件的输出级的电路级和可以形成在单个管芯（即，“PowerDie”）上并通过一个管芯彼此连接的低侧器件的电路级半导体衬底，并且还包括与低侧器件和高侧器件中的至少一个集成的肖特基二极管。高侧器件和低侧器件都可以包括横向扩散的金属氧化物半导体（LDMOS）晶体管。因为两个输出晶体管都包含相同类型的晶体管，所以可以同时形成两个器件，从而减少超过其它电压转换器设计的光掩模数量。电压转换器还可以包括在不同的管芯上的控制器电路，其可以与PowerDie电耦合并与其一体化。肖特基二极管的各种实施例可以提供肖特基保护和另外用于肖特基器件的JFET保护。

55. 发明申请

US20110068395A1 SUPER-SELF-ALIGNED TRENCH-DMOS STRUCTURE AND METHOD 有权
标题翻译：超自对准TRENCH-DMOS结构和方法
公开(公告)号：US20110068395A1
公开(公告)日：2011-03-24
申请号：US12958162
申请日：2010-12-01
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L29/78
CPC分类号： H01L29/66734 , H01L21/2257 , H01L29/04 , H01L29/0865 , H01L29/0869 , H01L29/41766 , H01L29/456 , H01L29/66727 , H01L29/7813
摘要： A semiconductor device includes a P-body layer formed in an N-epitaxial layer; a gate electrode formed in a trench in the P-body and N-epitaxial layer; a top source region formed from the P-body layer next to the gate electrode; a gate insulator disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the N-epitaxial layer; a cap insulator disposed on top of the gate electrode; and an N+ doped spacer disposed along a sidewall of the source and a sidewall of the gate insulator. The source includes N+ dopants diffused from the spacer. A body contact region containing P-type dopants is formed from the N-epitaxial layer. The contact region touches one or more P-doped regions of the P-body layer and the source. Methods for manufacturing such a device are also disclosed. Embodiments of this invention may also be applied to P-channel devices.
摘要翻译：半导体器件包括在N外延层中形成的P体层; 形成在P体和N外延层中的沟槽中的栅电极; 由栅极电极旁边的P体层形成的顶部源极区域; 沿着栅电极的侧壁设置在栅电极和源极之间，栅电极和P体之间以及栅电极和N外延层之间的栅极绝缘体; 设置在所述栅电极的顶部的盖绝缘体; 以及沿着源极的侧壁和栅极绝缘体的侧壁设置的N +掺杂的间隔物。源包括从间隔物扩散的N +掺杂剂。由N型外延层形成含有P型掺杂剂的体接触区域。接触区域接触P体层和源的一个或多个P掺杂区域。还公开了制造这种装置的方法。本发明的实施例也可以应用于P沟道器件。

56. 发明申请

US20100032751A1 SUPER-SELF-ALIGNED TRENCH-DMOS STRUCTURE AND METHOD 有权
标题翻译：超自对准TRENCH-DMOS结构和方法
公开(公告)号：US20100032751A1
公开(公告)日：2010-02-11
申请号：US12189062
申请日：2008-08-08
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66734 , H01L21/2257 , H01L29/04 , H01L29/0865 , H01L29/0869 , H01L29/41766 , H01L29/456 , H01L29/66727 , H01L29/7813
摘要： A semiconductor device includes a P-body layer formed in an N-epitaxial layer; a gate electrode formed in a trench in the P-body and N-epitaxial layer; a top source region formed from the P-body layer next to the gate electrode; a gate insulator disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the N-epitaxial layer; a cap insulator disposed on top of the gate electrode; and an N+ doped spacer disposed along a sidewall of the source and a sidewall of the gate insulator. The source includes N+ dopants diffused from the spacer. A body contact region containing P-type dopants is formed from the N-epitaxial layer. The contact region touches one or more P-doped regions of the P-body layer and the source. Methods for manufacturing such a device are also disclosed. Embodiments of this invention may also be applied to P-channel devices.
摘要翻译：半导体器件包括形成在N外延层中的P体层; 形成在P体和N外延层中的沟槽中的栅电极; 由栅极电极旁边的P体层形成的顶部源极区域; 沿着栅电极的侧壁设置在栅电极和源极之间，栅电极和P体之间以及栅电极和N外延层之间的栅极绝缘体; 设置在所述栅电极的顶部的盖绝缘体; 以及沿着源极的侧壁和栅极绝缘体的侧壁设置的N +掺杂的间隔物。源包括从间隔物扩散的N +掺杂剂。由N型外延层形成含有P型掺杂剂的体接触区域。接触区域接触P体层和源的一个或多个P掺杂区域。还公开了制造这种装置的方法。本发明的实施例也可以应用于P沟道器件。

57. 发明授权

US07646576B2 Apparatus and method for high-voltage transient blocking using low voltage elements 有权
标题翻译：使用低电压元件的高压瞬态阻塞的装置和方法
公开(公告)号：US07646576B2
公开(公告)日：2010-01-12
申请号：US11271059
申请日：2005-11-09
申请人： Richard A. Harris , Francois Hebert
发明人： Richard A. Harris , Francois Hebert
IPC分类号： H02H3/20 , H02H9/04
CPC分类号： H02H9/025 , H01L27/0266 , H01L27/0727 , H01L29/808 , H02H9/046
摘要： An apparatus and method for high-voltage transient blocking employing a transient blocking unit (TBU) that has at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device such that a transient alters a bias voltage Vp of the p-channel device and a bias voltage Vn of the n-channel device in concert. Specifically, the bias voltages are altered such that the p-channel device and n-channel device mutually switch off to block the transient. The depletion mode n-channel device employs a set of cascaded low-voltage depletion mode field effect transistors (FETs) such as metal-oxide-silicon field effect transistors (MOSFETs) connected source-to-drain to achieve the desired high-voltage operation of the TBU.
摘要翻译：一种用于使用具有与至少一个耗尽型p沟道器件互连的至少一个耗尽型n沟道器件的瞬态阻塞单元（TBU）的装置和方法，使得瞬态改变偏置电压Vp p沟道器件和n沟道器件的偏置电压Vn一致。具体地，改变偏置电压，使得p沟道器件和n沟道器件相互切断以阻止瞬变。耗尽型n沟道器件采用一组级联的低压耗尽型场效应晶体管（FET），例如连接源极到漏极的金属氧化物 - 硅场效应晶体管（MOSFET），以实现所需的高电压工作的TBU。

58. 发明申请

US20090263947A1 Bottom source LDMOSFET structure and method 有权
标题翻译：底源LDMOSFET结构和方法
公开(公告)号：US20090263947A1
公开(公告)日：2009-10-22
申请号：US12456949
申请日：2009-06-25
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L21/336
CPC分类号： H01L29/4175 , H01L21/26513 , H01L29/402 , H01L29/41766 , H01L29/41775 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/4941 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： This invention discloses a method to form a bottom-source lateral diffusion MOS (BS-LDMOS) device with a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The method includes a step of applying a sinker-channel mask for carrying out a deep sinker multiple energy implant to form a combined sinker-channel region in lower portion of an epitaxial layer to function as a buried source-body contact extending to and contacting a bottom of the substrate functioning as a bottom source electrode.
摘要翻译：本发明公开了一种形成底源横向扩散MOS（BS-LDMOS）器件的方法，源极区域设置在半导体衬底的顶表面附近的漏极区域的横向相对的位置，该半导体衬底在源极区域和漏极区域之间支撑栅极。该方法包括以下步骤：施加沉降通道掩模，用于进行深沉沉多次能量注入，以在外延层的下部形成组合沉降沟道区，以用作延伸到和接触的外部源体接触底部的底部用作底部源极。

59. 发明申请

US20080309442A1 Semiconductor power device having a stacked discrete inductor structure 有权
标题翻译：具有层叠离散电感器结构的半导体功率器件
公开(公告)号：US20080309442A1
公开(公告)日：2008-12-18
申请号：US11818219
申请日：2007-06-12
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： G05F1/62 , H01F27/06 , H01L23/48
CPC分类号： H01F27/292 , H01F17/0013 , H01F17/045 , H01F27/40 , H01F2007/1822 , H01L23/645 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/85 , H01L25/072 , H01L2224/0401 , H01L2224/05553 , H01L2224/16225 , H01L2224/16235 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48472 , H01L2224/48799 , H01L2224/49111 , H01L2224/49171 , H01L2224/81801 , H01L2224/85 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/12032 , H01L2924/1306 , H01L2924/14 , H01L2924/1461 , H01L2924/15173 , H01L2924/15174 , H01L2924/1532 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19107 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A power device includes a discrete inductor having contacts formed on a first surface of the discrete inductor and at least one semiconductor component mounted on the first surface of the discrete inductor and coupled to the contacts. The discrete inductor further includes contacts formed on a second surface opposite the first surface and routing connections connecting the first surface contacts to corresponding second surface contacts. The semiconductor components may be flip chip mounted onto the discrete inductor contacts or wire bonded thereto.
摘要翻译：功率器件包括具有形成在分立电感器的第一表面上的触点和安装在离散电感器的第一表面上并耦合到触点的至少一个半导体部件的分立电感器。离散电感器还包括形成在与第一表面相对的第二表面上的触点和将第一表面触点连接到对应的第二表面触点的路由连接。半导体部件可以倒装芯片安装到分立的电感器触头上或与之结合的引线上。

60. 发明申请

US20080265326A1 Structure and method for self protection of power device with expanded voltage ranges 有权
标题翻译：具有扩展电压范围的电力设备自保护的结构和方法
公开(公告)号：US20080265326A1
公开(公告)日：2008-10-30
申请号：US12156305
申请日：2008-05-31
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L23/62 , H02H9/00
CPC分类号： H01L23/3135 , H01L23/3121 , H01L23/62 , H01L24/40 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L2224/05553 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/0603 , H01L2224/40095 , H01L2224/40245 , H01L2224/48247 , H01L2224/48472 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/73221 , H01L2224/83801 , H01L2224/8385 , H01L2224/85 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01056 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13062 , H01L2924/13064 , H01L2924/13091 , H01L2924/181 , H01L2924/19043 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A vertical semiconductor power device includes a top surface and a bottom surface of a semiconductor substrate constituting a vertical current path for conducting a current there through. The semiconductor power device further includes an over current protection layer composed of a material having a resistance with a positive temperature coefficient (PTC) and the over current protection layer constituting as a part of the vertical current path connected to a source electrode and providing a feedback voltage a gate electrode of the vertical semiconductor power device for limiting a current passing there through for protecting the semiconductor power device at any voltage.
摘要翻译：垂直半导体功率器件包括构成用于在其通过的电流的垂直电流通路的半导体衬底的顶表面和底表面。半导体功率器件还包括由具有正温度系数（PTC）的电阻和过电流保护层构成的过电流保护层，该过电流保护层构成连接到源电极的垂直电流通路的一部分，并提供反馈电压垂直半导体功率器件的栅电极，用于限制通过其的电流，以在任何电压下保护半导体功率器件。

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