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51. 发明授权

US07482687B2 Etch stop in a damascene interconnect structure 失效
标题翻译：蚀刻停止在大马士革互连结构中
公开(公告)号：US07482687B2
公开(公告)日：2009-01-27
申请号：US11406499
申请日：2006-04-19
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L23/34
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813 , H01L23/5226 , H01L23/53223 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The low dielectric constant materials act as insulating layers through which trenches and vias are subsequently formed by employing a timed etching. Since the low dielectric constant materials are selected so that the etchant available for each one has only a small etch rate relative to the other low dielectric constant materials, the plurality of low dielectric constant materials act as etch stops during the fabrication of interconnect structures. This way, the etch stop layers employed in the prior art are eliminated and the number of fabrication steps is reduced.
摘要翻译：公开了具有作为蚀刻停止点的多个低介电常数绝缘层的互连结构。低介电常数材料充当绝缘层，通过采用定时蚀刻，通过该绝缘层形成沟槽和通孔。由于选择低介电常数材料，使得可用于每一种的蚀刻剂相对于其它低介电常数材料仅具有小的蚀刻速率，所以在制造互连结构期间，多种低介电常数材料用作蚀刻停止。这样，消除了现有技术中使用的蚀刻停止层，并减少了制造步骤的数量。

52. 发明授权

US07416958B2 Epitaxial semiconductor layer and method 有权
标题翻译：外延半导体层及方法
公开(公告)号：US07416958B2
公开(公告)日：2008-08-26
申请号：US11651159
申请日：2007-01-09
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L21/46 , H01L21/30 , H01L21/425
CPC分类号： H01L21/02573 , G02B6/43 , H01L21/0237 , H01L21/02381 , H01L21/02543 , H01L21/02546 , Y10S438/919
摘要： A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.
摘要翻译：提供一种用于外延形成附接到第二半导体结构的第一半导体结构的方法。所描述的器件和方法包括诸如两个不同半导体材料之间的外延界面处的晶格失配减小的优点。这种接口的一个有利应用包括电光通信结构。诸如在升高的温度下沉积层的方法可以容易地形成具有改进的晶格常数的半导体结构，这允许改进的外延界面。

53. 发明授权

US07335965B2 Packaging of electronic chips with air-bridge structures 有权
标题翻译：用气桥结构包装电子芯片
公开(公告)号：US07335965B2
公开(公告)日：2008-02-26
申请号：US10931510
申请日：2004-09-01
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L29/00 , H01L23/48
CPC分类号： H01L23/5329 , H01L21/7682 , H01L23/20 , H01L23/3677 , H01L23/4821 , H01L23/5222 , H01L23/66 , H01L2924/0002 , H01L2924/1433 , Y10S438/977 , H01L2924/00
摘要： A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structure embedded in a plurality of materials having a plurality of vaporization temperatures. The plurality of materials is formed on the electronic chip and the conductive structure is coupled to the electronic chip. To fabricate the circuit assembly, a support structure, including interstices, is formed on an electronic chip. The interstices of the support structure are filled with a material having a vaporization temperature that is less than the vaporization temperature of the support structure. Conductive structures are embedded in the support structure and the material, and a connective structure is mounted on the support structure. Finally, the material is removed from the interstices by heating the circuit assembly.
摘要翻译：一种用于制造空气桥结构的电路组件和制造能够支撑包括空气桥结构的电路组件的集成电路封装的方法。电路组件包括电子芯片和嵌入多个具有多个蒸发温度的材料中的导电结构。多个材料形成在电子芯片上，并且导电结构耦合到电子芯片。为了制造电路组件，在电子芯片上形成包括间隙的支撑结构。支撑结构的间隙填充有气化温度小于支撑结构的汽化温度的材料。导电结构嵌入在支撑结构和材料中，并且连接结构安装在支撑结构上。最后，通过加热电路组件从空隙中移除材料。

54. 发明授权

US07322511B2 Apparatus and method for printing micro metal structures 有权
标题翻译：用于印刷微型金属结构的装置和方法
公开(公告)号：US07322511B2
公开(公告)日：2008-01-29
申请号：US11232202
申请日：2005-09-21
申请人： Paul A. Farrar , Jerome M. Eldridge
发明人： Paul A. Farrar , Jerome M. Eldridge
IPC分类号： B23K31/02
CPC分类号： H01L21/288 , B23K1/0016 , B23K3/0607 , B23K2101/40 , H01L24/11 , H01L2224/13099 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01033 , H01L2924/01045 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/19043 , H05K3/3457 , H01L2224/0401
摘要： A method and device for printing liquid material such as liquid solder is provided. C4 structures as small as 10 microns in diameter can be produced using devices and methods described above. Further, devices and methods provided are able to operate at temperatures much higher than other print head designs such as piezoelectric actuated print heads. Additionally, due to the use of a gas flow restricting device and a recharging gas supply, ejection devices as described above can be used for a substantially extended lifetime, thus making devices and methods described above more economically desirable.
摘要翻译：提供了用于印刷诸如液体焊料的液体材料的方法和装置。可以使用上述装置和方法来生产直径小至10微米的C4结构。此外，所提供的装置和方法能够在比其他打印头设计（例如压电致动打印头）高得多的温度下操作。此外，由于使用气体流量限制装置和再充气气体供给，所以可以使用如上所述的喷射装置实质上延长的使用寿命，因此使上述装置和方法更经济上是理想的。

55. 发明授权

US07172949B2 Epitaxial semiconductor layer and method 有权
标题翻译：外延半导体层及方法
公开(公告)号：US07172949B2
公开(公告)日：2007-02-06
申请号：US10914292
申请日：2004-08-09
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L21/46 , H01L21/30 , H01L21/425
CPC分类号： H01L21/02573 , G02B6/43 , H01L21/0237 , H01L21/02381 , H01L21/02543 , H01L21/02546 , Y10S438/919
摘要： A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface.
摘要翻译：提供了一种用于外延形成附接到第二半导体结构的第一半导体结构的方法。所描述的器件和方法包括诸如两个不同半导体材料之间的外延界面处的晶格失配减小的优点。这种接口的一个有利应用包括电光通信结构。诸如在升高的温度下沉积层的方法可以容易地形成具有改进的晶格常数的半导体结构，这允许改进的外延界面。

56. 发明授权

US07157387B2 Techniques to create low K ILD for BEOL 有权
标题翻译：为BEOL创造低K ILD的技术
公开(公告)号：US07157387B2
公开(公告)日：2007-01-02
申请号：US10931182
申请日：2004-08-31
申请人： Arup Bhattacharyya , Paul A. Farrar
发明人： Arup Bhattacharyya , Paul A. Farrar
IPC分类号： H01L21/31
CPC分类号： H01L23/53295 , H01L21/02126 , H01L21/02203 , H01L21/02321 , H01L21/02337 , H01L21/02351 , H01L21/31695 , H01L21/7682 , H01L21/76825 , H01L23/5222 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at least one trench. After the metal layer is formed, voids are formed in the insulator layer. One aspect of the present subject matter relates to an integrated circuit. In various embodiments, the integrated circuit includes an insulator structure having a plurality of voids that have a maximum size, and a metal layer formed in the insulator structure. The maximum size of the voids is larger than the minimum photo dimension of the metal layer such that a maximum-sized void is capable of extending between a first and second metal line in the metal layer. Other aspects are provided herein.
摘要翻译：本主题的一个方面涉及形成层间电介质（ILD）的方法。在该方法的各种实施例中，形成绝缘体层，在绝缘体层中形成至少一个沟槽，并且在该至少一个沟槽中形成金属层。在形成金属层之后，在绝缘体层中形成空隙。本主题的一个方面涉及集成电路。在各种实施例中，集成电路包括具有多个具有最大尺寸的空隙的绝缘体结构和形成在绝缘体结构中的金属层。空隙的最大尺寸大于金属层的最小照片尺寸，使得最大尺寸的空隙能够在金属层中的第一和第二金属线之间延伸。本文提供了其他方面。

57. 发明授权

US07075166B1 Coating of copper and silver air bridge structures to improve electromigration resistance and other applications 失效
公开(公告)号：US07075166B1
公开(公告)日：2006-07-11
申请号：US10919903
申请日：2004-08-17
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L29/00
CPC分类号： H01L21/76838 , H01L21/7682 , H01L21/76834 , H01L21/7685 , H01L21/76852 , H01L23/5221 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air bridge extending through a gaseous medium so as to reduce the capacitance of the interconnect. The air bridge is supported at a first and second end such that the air bridge is suspended above the substrate. The air bridge comprises a highly conductive material, such as silver, so as to provide the air bridge with a reduced resistivity. To inhibit gaseous medium from contaminating the air bridge, the air bridge further comprises an adherent coating interposed between the air bridge and the gaseous medium. A method of forming the electrical interconnect is also disclosed, wherein, prior to forming the adherent coating, the conductive material is processed so as to form fewer grain boundaries, which enhances the electrical properties of the air bridge.

58. 发明授权

US07049219B1 Coating of copper and silver air bridge structures to improve electromigration resistance and other applications 失效
公开(公告)号：US07049219B1
公开(公告)日：2006-05-23
申请号：US10291909
申请日：2002-11-08
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/7682 , H01L21/76834 , H01L21/7685 , H01L21/76852 , H01L23/5221 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air bridge extending through a gaseous medium so as to reduce the capacitance of the interconnect. The air bridge is supported at a first and second end such that the air bridge is suspended above the substrate. The air bridge comprises a highly conductive material, such as silver, so as to provide the air bridge with a reduced resistivity. To inhibit gaseous medium from contaminating the air bridge, the air bridge further comprises an adherent coating interposed between the air bridge and the gaseous medium. A method of forming the electrical interconnect is also disclosed, wherein, prior to forming the adherent coating, the conductive material is processed so as to form fewer grain boundaries, which enhances the electrical properties of the air bridge.

59. 发明授权

US06979848B2 Memory system with conductive structures embedded in foamed insulator 失效
标题翻译：具有导电结构的存储系统嵌入发泡绝缘体
公开(公告)号：US06979848B2
公开(公告)日：2005-12-27
申请号：US10179091
申请日：2002-06-24
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/321 , H01L21/768 , H01L23/532 , H05K1/02 , H05K1/03 , H01L27/108
CPC分类号： H01L21/02126 , H01L21/02118 , H01L21/02282 , H01L21/02337 , H01L21/3105 , H01L21/31058 , H01L21/312 , H01L21/321 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H05K1/024 , H05K1/0346 , H01L2924/00
摘要： A conductive system and a method of forming an insulator for use in the conductive system is disclosed. The conductive system comprises a foamed polymer layer on a substrate. The foamed polymer layer has a surface that is hydrophobic, and a plurality of conductive structures are embedded in the foamed polymer layer. An insulator is formed by forming a polymer layer having a thickness on a substrate. The polymer layer is foamed to form a foamed polymer layer having a surface and a foamed polymer layer thickness, which is greater than the polymer layer thickness. The surface of the foamed polymer layer is treated to make the surface hydrophobic.
摘要翻译：公开了用于导电系统的导电系统和形成绝缘体的方法。导电系统包括在基底上的发泡聚合物层。发泡聚合物层具有疏水性的表面，并且多个导电结构嵌入发泡聚合物层中。通过在基板上形成厚度的聚合物层形成绝缘体。聚合物层被发泡以形成具有大于聚合物层厚度的表面和发泡聚合物层厚度的发泡聚合物层。处理发泡聚合物层的表面以使表面疏水。

60. 发明授权

US06949839B2 Aligned buried structures formed by surface transformation of empty spaces in solid state materials 失效
标题翻译：通过固体材料中的空白空间的表面变换形成的对齐掩埋结构
公开(公告)号：US06949839B2
公开(公告)日：2005-09-27
申请号：US10277043
申请日：2002-10-22
申请人： Paul A. Farrar , Joseph E. Geusic
发明人： Paul A. Farrar , Joseph E. Geusic
IPC分类号： G03F9/00 , H01L21/764 , H01L23/544 , H01L23/48
CPC分类号： H01L21/3247 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/764 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S257/92 , Y10S438/975 , H01L2924/00
摘要： A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are formed to include a conductive material having a melting temperature higher than an annealing temperature used to form such empty-spaced buried patterns. The high-temperature metal marks are formed prior to the formation of the empty-spaced buried patterns formed in a monocrystalline substrate, so that the empty-space buried patterns are aligned to the marks. Subsequent semiconductor structures that are formed as part of desired semiconductor devices can be also aligned to the marks.
摘要翻译：公开了一种对准在半导体单晶衬底中形成的多个空间间隔的掩模图案的方法。在示例性实施例中，形成高温金属标记以包括具有高于用于形成这样的空间间隔掩埋图案的退火温度的熔化温度的导电材料。在形成在单晶衬底中形成的空间间隔的掩模图形之前形成高温金属标记，使得空间掩埋图案与标记对准。形成为期望的半导体器件的一部分的后续半导体结构也可以与标记对准。

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