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51. 发明申请

US20100245328A1 STORAGE CAPACITOR LINE DRIVE CIRCUIT AND DISPLAY DEVICE 有权
标题翻译：存储电容器线路驱动电路和显示设备
公开(公告)号：US20100245328A1
公开(公告)日：2010-09-30
申请号：US12734376
申请日：2008-08-21
申请人： Yasushi Sasaki , Yuhichiroh Murakami , Makoto Yokoyama , Shige Furuta
发明人： Yasushi Sasaki , Yuhichiroh Murakami , Makoto Yokoyama , Shige Furuta
IPC分类号： G09G5/00
CPC分类号： G09G3/3655 , G09G3/3614 , G09G3/3677 , G09G2300/0876 , G09G2310/0286 , G09G2320/0209 , G09G2320/0219 , G11C19/184
摘要： In a storage capacitor line drive circuit driving a storage capacitor line of an active-matrix display device and driven by outputs of a scanning signal line drive circuit, at least one (VSS) of a high-potential supply voltage (VDD) and a low-potential supply voltage (VSS) differs from a supply voltage (GVSS) of a corresponding logical level of the scanning signal line drive circuit, the high-potential supply voltage and the low-potential supply voltage being used for generating a signal voltage of a preceding stage to an output stage. This makes it possible to achieve a storage capacitor line drive circuit capable of avoiding malfunctioning even in a case where the storage capacitor line drive circuit receives noise from a scanning signal line, and a display device including the storage capacitor line drive circuit.
摘要翻译：在驱动有源矩阵型显示装置的辅助电容线并由扫描信号线驱动电路的输出驱动的辅助电容线驱动电路中，高电位电源电压（VDD）和低电位电位电压（VSS）与扫描信号线驱动电路的相应逻辑电平的电源电压（GVSS）不同，高电位电源电压和低电位电源电压用于产生信号电压前一阶段到产出阶段。这使得即使在存储电容器线路驱动电路从扫描信号线接收到噪声的情况下也可以实现能够避免故障的存储电容器线路驱动电路，以及包括辅助电容线驱动电路的显示装置。

52. 发明申请

US20100244946A1 SEMICONDUCTOR DEVICE AND DISPLAY DEVICE 有权
标题翻译：半导体器件和显示器件
公开(公告)号：US20100244946A1
公开(公告)日：2010-09-30
申请号：US12734044
申请日：2008-08-26
申请人： Yuhichiroh Murakami , Yasushi Sasaki , Shige Furuta
发明人： Yuhichiroh Murakami , Yasushi Sasaki , Shige Furuta
IPC分类号： H01L25/00
CPC分类号： G09G3/3677 , G09G3/3655 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G11C19/184 , G11C19/28 , H03K17/063 , H03K17/165 , H03K17/693
摘要： A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal. Therefore, it is possible to provide: a semiconductor device constituted by transistors of the same conductivity type, which semiconductor device can output a stable signal by preventing a reduction in electric potential level; and a display device including the semiconductor device.
摘要翻译：电路由多个n沟道型晶体管构成，所述电路包括：在所述多个晶体管中，包括用于接收VDD电压的漏极端子的晶体管，源极端子和用于接收输入的栅极端子信号; 在多个晶体管中，包括用于接收VDD的电压的漏极端子，连接到输出端子的源极端子和连接到晶体管的源极端子的栅极端子的晶体管; 以及设置在节点和时钟端子之间用于接收时钟信号的电容器。在至少一个实施例中，输入到时钟端的时钟信号的频率高于从输出端输出的输出信号的频率。因此，可以提供：由相同导电类型的晶体管构成的半导体器件，该半导体器件可以通过防止电位电平的降低而输出稳定的信号; 以及包括半导体器件的显示装置。

53. 发明申请

US20100214206A1 SHIFT REGISTER 有权
标题翻译：移位寄存器
公开(公告)号：US20100214206A1
公开(公告)日：2010-08-26
申请号：US12734218
申请日：2008-08-26
申请人： Makoto Yokoyama , Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki
发明人： Makoto Yokoyama , Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki
IPC分类号： G09G3/36 , G11C19/00
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/06 , G09G2330/08 , G11C19/28
摘要： At least one embodiment the present invention a plurality of unit circuits connected in multiple stages, to normal operation when the unit circuits are simultaneously turned on to output high-level output signals. When a shift register malfunctions, so that output signals provided by previous- and subsequent-stage unit circuits are simultaneously set to high level, malfunction restoration circuits and included in a unit circuit detect the malfunction in at least one embodiment. The malfunction restoration circuit provides a high voltage to a node, thereby forcibly pulling down an output signal. Also, the malfunction restoration circuit forcibly discharges another node, so that a charge accumulated in a capacitance is released. As a result, the shift register in malfunction can be instantaneously restored to normal operation. At least one embodiment of the present invention is suitable for driver circuits or suchlike of display devices and imaging devices.
摘要翻译：本发明的至少一个实施例是多个单元电路以多级连接，当单元电路同时导通以输出高电平输出信号时，进行正常操作。当移位寄存器发生故障时，使得由前一级和后级单元电路提供的输出信号同时设置为高电平，故障恢复电路并包括在单元电路中，在至少一个实施例中检测故障。故障恢复电路向节点提供高电压，从而强制拉下输出信号。此外，故障恢复电路强制地对另一个节点进行放电，从而释放在电容中累积的电荷。结果，故障中的移位寄存器可以立即恢复正常运行。本发明的至少一个实施例适用于诸如显示装置和成像装置的驱动电路等。

54. 发明申请

US20100141642A1 SHIFT REGISTER 有权
标题翻译：移位寄存器
公开(公告)号：US20100141642A1
公开(公告)日：2010-06-10
申请号：US12733119
申请日：2008-05-15
申请人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
发明人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
IPC分类号： G09G5/00 , G11C19/00
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.
摘要翻译：在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。通过使用高电平周期彼此不重叠的两相时钟信号，复位信号生成电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平高层次。在复位信号处于高电平的期间，晶体管执行节点的放电和输出信号的下拉。因此，可以获得执行节点放电和输出信号下拉的移位寄存器，并且在不使用来自后续电路的输出信号的情况下实现小面积和低功耗。

55. 发明授权

US08952955B2 Display driving circuit, display device and display driving method 有权
标题翻译：显示驱动电路，显示装置及显示驱动方式
公开(公告)号：US08952955B2
公开(公告)日：2015-02-10
申请号：US13375778
申请日：2010-02-23
申请人： Makoto Yokoyama , Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta
发明人： Makoto Yokoyama , Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta
IPC分类号： G06F3/038 , G09G3/36
CPC分类号： G09G3/3655 , G09G3/3614 , G09G3/3677 , G09G2300/0852 , G09G2300/0876
摘要： A display driving circuit for driving a liquid crystal display panel includes a shift register including a plurality of shift register circuits provided in such a way as to correspond to a plurality of gate lines, respectively, the display driving circuit having latch circuits provided in such a way as to correspond one-by-one to the shift register circuits, a polarity signal being inputted to the latch circuits. When a internal signal generated by a shift register circuit becomes active, a latch circuit loads and retains the polarity signal, and an output from the latch circuit is supplied to a CS bus line. The internal signal becomes active before a first vertical scanning period of a display picture.
摘要翻译：用于驱动液晶显示面板的显示驱动电路包括移位寄存器，该移位寄存器包括分别以与多个栅极线相对应的方式设置的多个移位寄存器电路，显示驱动电路具有设置在这种方式一对一地对应到移位寄存器电路，极性信号被输入到锁存电路。当由移位寄存器电路产生的内部信号变为有效时，锁存电路加载并保持极性信号，并且将锁存电路的输出提供给CS总线。内部信号在显示图像的第一垂直扫描周期之前变为有效。

56. 发明授权

US08718223B2 Semiconductor device and display device 有权
标题翻译：半导体器件和显示器件
公开(公告)号：US08718223B2
公开(公告)日：2014-05-06
申请号：US12734044
申请日：2008-08-26
申请人： Yuhichiroh Murakami , Yasushi Sasaki , Shige Furuta
发明人： Yuhichiroh Murakami , Yasushi Sasaki , Shige Furuta
IPC分类号： G11C19/00
CPC分类号： G09G3/3677 , G09G3/3655 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G11C19/184 , G11C19/28 , H03K17/063 , H03K17/165 , H03K17/693
摘要： A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal. Therefore, it is possible to provide: a semiconductor device constituted by transistors of the same conductivity type, which semiconductor device can output a stable signal by preventing a reduction in electric potential level; and a display device including the semiconductor device.
摘要翻译：电路由多个n沟道型晶体管构成，所述电路包括：在所述多个晶体管中，包括用于接收VDD电压的漏极端子的晶体管，源极端子和用于接收输入的栅极端子信号; 在多个晶体管中，包括用于接收VDD的电压的漏极端子，连接到输出端子的源极端子和连接到晶体管的源极端子的栅极端子的晶体管; 以及设置在节点和时钟端子之间用于接收时钟信号的电容器。在至少一个实施例中，输入到时钟端的时钟信号的频率高于从输出端输出的输出信号的频率。因此，可以提供：由相同导电类型的晶体管构成的半导体器件，该半导体器件可以通过防止电位电平的降低而输出稳定的信号; 以及包括半导体器件的显示装置。

57. 发明授权

US08457272B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08457272B2
公开(公告)日：2013-06-04
申请号：US12734218
申请日：2008-08-26
申请人： Makoto Yokoyama , Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki
发明人： Makoto Yokoyama , Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki
IPC分类号： G11C19/00
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/06 , G09G2330/08 , G11C19/28
摘要： At least one embodiment the present invention a plurality of unit circuits connected in multiple stages, to normal operation when the unit circuits are simultaneously turned on to output high-level output signals. When a shift register malfunctions, so that output signals provided by previous- and subsequent-stage unit circuits are simultaneously set to high level, malfunction restoration circuits and included in a unit circuit detect the malfunction in at least one embodiment. The malfunction restoration circuit provides a high voltage to a node, thereby forcibly pulling down an output signal. Also, the malfunction restoration circuit forcibly discharges another node, so that a charge accumulated in a capacitance is released. As a result, the shift register in malfunction can be instantaneously restored to normal operation. At least one embodiment of the present invention is suitable for driver circuits or suchlike of display devices and imaging devices.
摘要翻译：本发明的至少一个实施例是多个单元电路以多级连接，当单元电路同时导通以输出高电平输出信号时，进行正常操作。当移位寄存器发生故障时，使得由前一级和后级单元电路提供的输出信号同时设置为高电平，故障恢复电路并包括在单元电路中，在至少一个实施例中检测故障。故障恢复电路向节点提供高电压，从而强制拉下输出信号。此外，故障恢复电路强制地对另一个节点进行放电，从而释放在电容中累积的电荷。结果，故障中的移位寄存器可以立即恢复正常运行。本发明的至少一个实施例适用于诸如显示装置和成像装置的驱动电路等。

58. 发明授权

US08395419B2 Semiconductor device and display device 有权
公开(公告)号：US08395419B2
公开(公告)日：2013-03-12
申请号：US12734044
申请日：2008-08-26
申请人： Yuhichiroh Murakami , Yasushi Sasaki , Shige Furuta
发明人： Yuhichiroh Murakami , Yasushi Sasaki , Shige Furuta
IPC分类号： H03B1/00
摘要： A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal. Therefore, it is possible to provide: a semiconductor device constituted by transistors of the same conductivity type, which semiconductor device can output a stable signal by preventing a reduction in electric potential level; and a display device including the semiconductor device.

59. 发明申请

US20120307959A1 SHIFT REGISTER 有权
标题翻译：移位寄存器
公开(公告)号：US20120307959A1
公开(公告)日：2012-12-06
申请号：US13571608
申请日：2012-08-10
申请人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
发明人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
IPC分类号： G11C19/00
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译：在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平进入高层。在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。

60. 发明授权

US08269714B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08269714B2
公开(公告)日：2012-09-18
申请号：US12733119
申请日：2008-05-15
申请人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
发明人： Shige Furuta , Yuhichiroh Murakami , Yasushi Sasaki , Shinsaku Shimizu
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.
摘要翻译：在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。通过使用高电平周期彼此不重叠的两相时钟信号，复位信号生成电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平高层次。在复位信号处于高电平的期间，晶体管执行节点的放电和输出信号的下拉。因此，可以获得执行节点放电和输出信号下拉的移位寄存器，并且在不使用来自后续电路的输出信号的情况下实现小面积和低功耗。

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