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51. 发明授权

US06908817B2 Flash memory array with increased coupling between floating and control gates 失效
标题翻译：闪存阵列具有增加的浮动和控制门之间的耦合
公开(公告)号：US06908817B2
公开(公告)日：2005-06-21
申请号：US10268635
申请日：2002-10-09
申请人： Jack H. Yuan
发明人： Jack H. Yuan
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11526 , H01L27/11543 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control gate that wraps around it, thereby increasing the coupling between the two. In another form, an erase gate wraps around a relatively small projection in order to take advantage of sharp edges of the projection to promote tunneling of electrons from the floating to the erase gate. In each case, the control or floating gate is positioned within the area of the floating gate in one direction, thereby not requiring additional substrate area for such memory cells.
摘要翻译：公开了浮动栅极结构，其具有与基底耦合的基极区域和从基底远离基底延伸的窄突起。在一种形式中，相对大的突起的表面为包围其的控制栅提供增加的表面积，从而增加两者之间的耦合。在另一种形式中，擦除栅极围绕相对较小的突起卷绕，以便利用突起的尖锐边缘来促进电子从浮动栅极到擦除栅极的隧穿。在每种情况下，控制或浮动栅极在一个方向上位于浮动栅极的区域内，从而不需要这种存储器单元的附加衬底区域。

52. 发明授权

US06723604B2 Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming 有权
公开(公告)号：US06723604B2
公开(公告)日：2004-04-20
申请号：US10265066
申请日：2002-10-03
申请人： Jack H. Yuan , Jacob Haskell
发明人： Jack H. Yuan , Jacob Haskell
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0458 , H01L27/115 , H01L27/11524 , H01L29/66825 , H01L29/7887
摘要： Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

53. 发明授权

US5712179A Method of making triple polysilicon flash EEPROM arrays having a separate erase gate for each row of floating gates 失效
标题翻译：制造具有用于每行浮动栅极的单独的擦除栅极的三重多晶硅快闪EEPROM阵列的方法
公开(公告)号：US5712179A
公开(公告)日：1998-01-27
申请号：US550887
申请日：1995-10-31
申请人： Jack H. Yuan
发明人： Jack H. Yuan
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： As part of a flash EEPROM array on a semiconductor substrate, erase gates are formed in individual trenches between rows of floating gates. The erase gate is positioned along one sidewall of the trench in a manner to be capacitively coupled with the floating gates of one of the rows adjacent the trench but spaced apart from the floating gates of the other row adjacent the trench. In this way, a separate erase gate is provided for each row of floating gates without increasing the size of the array. The erasure of each row can then be individually controlled. Two self-aligned methods of forming such an array are disclosed. One method involves forming a thick insulating layer along one sidewall of the trench and then filling a remaining space adjacent an opposite trench sidewall with polysilicon material forming an erase gate for the row of floating gates adjacent the other sidewall. A second method involves anisotropically etching a layer of polysilicon that is formed over the array in a manner to conform to the trench sidewalls, thereby separating the polysilicon layer into individual erase gates carried by the trench sidewalls.
摘要翻译：作为半导体衬底上的快闪EEPROM阵列的一部分，擦除栅极形成在浮动栅极行之间的各个沟槽中。擦除栅极以沟槽的一个侧壁定位，以便与邻近沟槽的行中的一个的浮动栅极电容耦合，但是与邻近沟槽的另一个行的浮动栅极间隔开。以这种方式，为每行浮动栅极提供单独的擦除栅极，而不增加阵列的尺寸。然后可以单独控制每行的擦除。公开了形成这种阵列的两种自对准方法。一种方法包括沿着沟槽的一个侧壁形成厚的绝缘层，然后用邻近另一个侧壁的浮动栅极行的多晶硅材料填充与相对的沟槽侧壁相邻的剩余空间。第二种方法包括以符合沟槽侧壁的方式各向异性地蚀刻在阵列上形成的多晶硅层，从而将多晶硅层分离成由沟槽侧壁承载的各个擦除栅极。

54. 发明授权

US5661053A Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers 失效
标题翻译：使用间隔物制造在沉积的场氧化物中形成密集的快速EEPROM单元阵列和外围支撑电路的方法
公开(公告)号：US5661053A
公开(公告)日：1997-08-26
申请号：US248735
申请日：1994-05-25
申请人： Jack H. Yuan
发明人： Jack H. Yuan
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L27/11534 , H01L27/11543 , Y10S438/917 , Y10S438/947
摘要： Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.
摘要翻译：形成具有单个电池尺寸的快闪EEPROM单元阵列的技术被减少，从而增加可能形成在给定尺寸的半导体衬底上的电池数量。在该过程的几个步骤中使用电介质间隔物控制正被蚀刻或注入离子的区域，使之比通过最高分辨率光刻可以获得的更小。包括分离通道和非分离通道（无选择晶体管）类型的存储单元。示例单元采用具有分离的浮置，控制和擦除栅极的三个多晶硅层。形成具有较高导电性均匀性的存储单元栅极的技术包括沉积未掺杂的多晶硅，然后使用离子注入来引入掺杂剂。通过CVD沉积和干蚀刻在该工艺的早期阶段形成场氧化物。存储单元阵列和相邻的外围组件以协调的方式形成在单个集成电路芯片上。

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