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51. 发明申请

US20050057966A1 Boosted substrate/tub programming for flash memories 有权
公开(公告)号：US20050057966A1
公开(公告)日：2005-03-17
申请号：US10663277
申请日：2003-09-16
申请人： Hagop Nazarian
发明人： Hagop Nazarian
IPC分类号： G11C11/34 , G11C16/04 , G11C16/12
CPC分类号： G11C16/12 , G11C16/0483
摘要： A boosted substrate tub/substrate floating gate memory cell programming process is described that applies a voltage to the substrate or substrate “tub” of a NAND Flash memory array to precharge a channel of carriers within the floating gate memory cells prior to applying a high gate programming voltage to the gate of the selected floating gate memory cells and coupling a program or program-inhibit voltage to program the selected floating gate memory cell(s) as desired. The use of a boosted tub programming approach avoids the requirement that the bitline and/or source line circuit design of the NAND Flash array be able to withstand or carry high voltages during programming of a floating gate memory cells and allows reuse of the block erase high voltage circuits connected to the substrate tub. This allows the NAND Flash memory array to be designed with smaller circuit designs and/or smaller circuit feature elements.

52. 发明申请

US20050002218A1 Sensing scheme for programmable resistance memory using voltage coefficient characteristics 有权
公开(公告)号：US20050002218A1
公开(公告)日：2005-01-06
申请号：US10610800
申请日：2003-07-02
申请人： Hagop Nazarian
发明人： Hagop Nazarian
IPC分类号： G11C11/00 , G11C11/15 , G11C11/16
CPC分类号： G11C13/004 , G11C11/16 , G11C2013/0057
摘要： A method and apparatus for sensing the resistance state of data in a resistance memory cell by using the voltage coefficient of the cell instead of only its resistance. A voltage potential is applied across the resistance memory cell allowing the voltage coefficient of the cell to be determined and subsequently used to determine the logic state of the cell.

53. 再颁专利

USRE37577E1 High speed configuration independent programmable macrocell 失效
标题翻译：高速配置独立的可编程宏单元
公开(公告)号：USRE37577E1
公开(公告)日：2002-03-12
申请号：US09047314
申请日：1998-03-24
申请人： Lin-Shih Liu , Syed Babar Raza , Hagop Nazarian , George M. Ansel , Stephen M. Douglass , Jeffrey Scott Hunt
发明人： Lin-Shih Liu , Syed Babar Raza , Hagop Nazarian , George M. Ansel , Stephen M. Douglass , Jeffrey Scott Hunt
IPC分类号： H03K19173
CPC分类号： H03K19/1736
摘要： A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.
摘要翻译：用户可配置电路包含时钟逻辑，开关元件和数据路径电路。在开关元件中接收输入数据，并且开关元件和数据路径电路构成电路的整个数据路径。接收多个用户可配置输入以为特定用户应用配置电路。时钟逻辑和开关元件实现可由用户可配置输入配置的逻辑功能。逻辑功能在时钟逻辑中被预处理，从而在数据通路中发生最小的延迟。此外，通过开关元件和寄存器的传播延迟与用户可配置输入无关。本发明的用户可配置电路具有用作可编程逻辑器件的宏小区的应用，允许用户将电路配置为D型触发器，T型触发器。此外，用户选择输出电路的极性。

54. 发明授权

US6100752A Method and apparatus for reducing power supply current surges in a charge pump using a delayed clock line 失效
标题翻译：使用延迟的时钟线减少电荷泵中的电源电流浪涌的方法和装置
公开(公告)号：US6100752A
公开(公告)日：2000-08-08
申请号：US928716
申请日：1997-09-12
申请人： May Lee , Lawrence D. Engh , Hagop Nazarian
发明人： May Lee , Lawrence D. Engh , Hagop Nazarian
IPC分类号： H02M3/07 , H03K3/01
CPC分类号： H02M3/07
摘要： The present invention is a charge pump circuit to reduce and distribute power supply current surges. The charge pump circuit includes a first clock line to provide a first clock thereon, a plurality of delay circuits connected in series, each delay circuit generating a delayed and inverted clock from its input clock on a respective output clock line, and a plurality of charge pump stages connected in series each to store charge thereon. The first clock line is coupled to the first charge pump stage and the plurality of output clock lines are coupled to a respective plurality of remaining charge pump stages. The operation of each charge pump stage is staggered to reduce and distribute the power supply current surges.
摘要翻译：本发明是一种用于减少和分配电源电流浪涌的电荷泵电路。电荷泵电路包括：第一时钟线，用于提供第一时钟，串联连接的多个延迟电路，每个延迟电路从相应输出时钟线上的输入时钟产生延迟和反相时钟，以及多个充电泵级分别串联连接以在其上存储电荷。第一时钟线耦合到第一电荷泵级，并且多个输出时钟线耦合到相应的多个剩余电荷泵级。每个电荷泵级的操作是交错的，以减少和分配电源电流浪涌。

55. 发明授权

US5654652A High-speed ratio CMOS logic structure with static and dynamic pullups and/or pulldowns using feedback 失效
标题翻译：具有静态和动态上拉和/或下拉使用反馈的高速比CMOS逻辑结构
公开(公告)号：US5654652A
公开(公告)日：1997-08-05
申请号：US534358
申请日：1995-09-27
申请人： S. Babar Raza , Hagop Nazarian
发明人： S. Babar Raza , Hagop Nazarian
IPC分类号： H03K19/003 , H03K19/017 , H03K19/0948
CPC分类号： H03K19/00361
摘要： A high speed ratio CMOS logic structure includes a static PMOS pullup transistor connected to an output node, and a plurality of NMOS pulldown transistors, connected in parallel, to the output node and which collectively define a pulldown circuit. The pullup transistor is biased using a reference voltage to define a static pullup strength for the logic structure. The pulldown strength of the pulldown circuit is also fixed. The combination of the pullup transistor, and the pulldown transistors define an N input NOR gate. The logic structure, however, further includes a feedback logic circuit, formed by a pair of inverters connected in series coupled to the output node to sense a current logic state of the output node. The feedback logic circuit generates an enable signal that is provided to a second, dynamic PMOS transistor connected in parallel with the static pullup PMOS transistor. When the logic state on the output node is low, the feedback logic circuit generates a low signal, which activates the dynamic PMOS transistor into a conductive state, thus increasing the pullup strength of the logic structure. This increased pullup strength provides for an improved switching for the next logic state transition: low-to-high. Once the output node has transitioned to the logic high state, and after a fixed time delay, the feedback logic circuit generates a logic high signal, which turns off the dynamic PMOS transistor, which weakens the pullup strength of the logic structure. In view of this weakened pullup strength, the next logic state transition of the output node--high-to-low--is accomplished much faster.
摘要翻译：高速比CMOS逻辑结构包括连接到输出节点的静态PMOS上拉晶体管和并联连接到输出节点并且共同定义下拉电路的多个NMOS下拉晶体管。使用参考电压对上拉晶体管进行偏置，以定义逻辑结构的静态上拉强度。下拉电路的下拉强度也是固定的。上拉晶体管和下拉晶体管的组合限定了N个输入NOR门。然而，逻辑结构还包括反馈逻辑电路，其由串联耦合到输出节点的一对反相器形成，以感测输出节点的当前逻辑状态。反馈逻辑电路产生提供给与静态上拉PMOS晶体管并联连接的第二动态PMOS晶体管的使能信号。当输出节点上的逻辑状态为低电平时，反馈逻辑电路产生一个低电平信号，这个信号将动态PMOS晶体管激活成导通状态，从而增加了逻辑结构的上拉电阻。这种增加的上拉强度为下一个逻辑状态转换提供了一个改进的切换：从低到高。一旦输出节点转变到逻辑高电平状态，并且在固定的时间延迟之后，反馈逻辑电路产生逻辑高电平信号，这将关闭动态PMOS晶体管，这削弱了逻辑结构的上拉电阻。鉴于这种上拉强度的削弱，输出节点的下一个逻辑状态转换 - 从高到低实现得快得多。

56. 发明授权

US5467029A OR array architecture for a programmable logic device 失效
标题翻译： OR阵列架构可编程逻辑器件
公开(公告)号：US5467029A
公开(公告)日：1995-11-14
申请号：US144663
申请日：1993-10-28
申请人： Norman P. Taffe , Stephen M. Douglass , Hagop Nazarian
发明人： Norman P. Taffe , Stephen M. Douglass , Hagop Nazarian
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17708
摘要： An OR array including a first multiplicity of OR devices, to which a second multiplicity of product term signals are variably distributed. Some product term signals are distributed to four OR devices, other product term signals are distributed two or three OR devices, and still other product term signals are distributed to only one OR device.
摘要翻译：包括第一多个OR器件的OR阵列，第二多个乘积项信号被可变地分布到该OR器件。一些产品术语信号分配到四个OR设备，其他产品术语信号分配两个或三个OR设备，而其他产品术语信号仅分发给一个OR设备。

57. 发明授权

US08832408B2 Non-volatile memory array partitioning architecture and method to utilize single level cells and multi-level cells within the same memory 有权
标题翻译：非易失性存储器阵列分区体系结构和方法利用同一个存储器内的单级单元和多级单元
公开(公告)号：US08832408B2
公开(公告)日：2014-09-09
申请号：US11928865
申请日：2007-10-30
申请人： Hagop Nazarian , Ali Pourkeramati
发明人： Hagop Nazarian , Ali Pourkeramati
IPC分类号： G06F12/00 , G11C16/08 , G11C11/56
CPC分类号： G11C11/5621 , G11C16/08 , G11C2211/5641
摘要： A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode.
摘要翻译：公开了一种存储器件，并且包括存储器单元阵列和配置成以单级单元模式寻址阵列的第一部分的分区系统，以及以多级单元模式的阵列的第二部分。

58. 发明授权

US08404553B2 Disturb-resistant non-volatile memory device and method 有权
标题翻译：抗干扰的非易失性存储器件及方法
公开(公告)号：US08404553B2
公开(公告)日：2013-03-26
申请号：US12861666
申请日：2010-08-23
申请人： Scott Brad Herner , Hagop Nazarian
发明人： Scott Brad Herner , Hagop Nazarian
IPC分类号： H01L21/20
CPC分类号： H01L27/2463 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1253 , H01L45/14 , H01L45/148 , H01L45/1608 , H01L45/1675
摘要： A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction. The first strip of switching material, the second strip of switching material, the contact material, and the first wiring material are subjected to a second patterning and etching process to form at least a first switching element from the first strip of switching material and at least a second switching element from the second strip of switching material, and a first wiring structure comprising at least the first wiring material and the contact material. The first wiring structure being is in a second direction at an angle to the first direction.
摘要翻译：一种形成抗干扰非易失性存储器件的方法。该方法包括提供具有表面区域并形成覆盖表面区域的第一电介质材料的半导体衬底。第一布线材料覆盖在第一介电材料上，掺杂多晶硅材料覆盖在第一布线材料上，非晶硅开关材料覆盖在所述多晶硅材料上。对开关材料进行第一图案化和蚀刻工艺，以将第一条开关材料与在第一方向上空间取向的第二开关条分离。第一切换材料条，第二条切换材料，接触材料和第一布线材料经受第二图案化和蚀刻工艺，以从第一条开关材料形成至少第一开关元件，并且至少来自所述第二开关材料条的第二开关元件，以及至少包括所述第一布线材料和所述接触材料的第一布线结构。第一布线结构处于与第一方向成一定角度的第二方向。

59. 发明申请

US20120327701A1 MEMORY ARRAY ARCHITECTURE WITH TWO-TERMINAL MEMORY CELLS 有权
标题翻译：具有两个终端记忆细胞的记忆阵列结构
公开(公告)号：US20120327701A1
公开(公告)日：2012-12-27
申请号：US13529985
申请日：2012-06-21
申请人： Hagop Nazarian
发明人： Hagop Nazarian
IPC分类号： H01L47/00 , G11C11/00
CPC分类号： G11C11/1659 , G11C8/14 , G11C11/1653 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2213/33 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2213/82 , H01L27/228 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/148
摘要： A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.
摘要翻译：非易失性存储器件包括沿着第一方向延伸的字线; 沿第二方向延伸的位线; 具有耦合到位线的读取晶体管，至少一个两端存储单元和选择晶体管的存储单元，所述双端存储单元具有耦合到字线的第一端和耦合到栅极的第二端的读取晶体管。双端存储单元的第二端耦合到由选择晶体管的漏极和读取晶体管的栅极共享的公共节点。

60. 发明授权

US08296626B2 Error correction for flash memory 有权
标题翻译：闪存的错误更正
公开(公告)号：US08296626B2
公开(公告)日：2012-10-23
申请号：US12267017
申请日：2008-11-07
申请人： Hagop Nazarian , Ping Hou
发明人： Hagop Nazarian , Ping Hou
IPC分类号： G11C29/00
CPC分类号： G06F11/1072 , G11C2029/0411
摘要： Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.
摘要翻译：本文描述了提供电子存储器的单位和多位纠错。作为示例，可以通过在一组分析的存储器单元的位级分布之间建立可疑区域来实现纠错。可疑区域可以定义分布的潜在错误位。如果对于分布检测到位错误，则可以首先将错误校正应用于可疑区域中的潜在错误位。通过识别怀疑的错误位并将初始误差修正限制在这种识别的位上，可以减轻或避免对分布的所有位应用纠错所涉及的复杂性，从而提高电子存储器误码校正的效率。

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