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51. 发明授权

US08995175B1 Memory circuit with PMOS access transistors 有权
标题翻译：具有PMOS存取晶体管的存储电路
公开(公告)号：US08995175B1
公开(公告)日：2015-03-31
申请号：US13350575
申请日：2012-01-13
申请人： Jun Liu , Irfan Rahim , Yanzhong Xu , Andy L. Lee
发明人： Jun Liu , Irfan Rahim , Yanzhong Xu , Andy L. Lee
IPC分类号： G11C11/412 , G11C5/14
CPC分类号： G11C5/14 , G11C11/412 , G11C11/418
摘要： A memory circuit that includes a memory storage unit and access transistors coupled to the memory storage unit, where the access transistors include PMOS transistors, is described. In one implementation, the memory circuit further includes a bias clamp transistor coupled to the memory storage unit.
摘要翻译：描述了一种存储器电路，其包括存储器存储单元和耦合到存储器存储单元的存取晶体管，其中存取晶体管包括PMOS晶体管。在一个实现中，存储器电路还包括耦合到存储器存储单元的偏置钳位晶体管。

52. 发明授权

US08732635B2 Apparatus and methods for power management in integrated circuits 有权
标题翻译：集成电路中电源管理的装置和方法
公开(公告)号：US08732635B2
公开(公告)日：2014-05-20
申请号：US12165665
申请日：2008-07-01
申请人： David Lewis , Christopher F. Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
发明人： David Lewis , Christopher F. Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
IPC分类号： G06F17/50 , G06F9/455 , H03K3/01 , G05F1/10
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
摘要翻译：可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。控制电路耦合到非易失性存储器和配置存储器。一组电压从控制电路的输出导出，并被应用于PLD内的电路。

53. 发明授权

US08487651B2 Multiple data rate memory interface architecture 有权
公开(公告)号：US08487651B2
公开(公告)日：2013-07-16
申请号：US13176284
申请日：2011-07-05
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/173
CPC分类号： G11C7/10 , H03K19/17744
摘要： The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.

54. 发明授权

US08305121B1 High-performance memory interface circuit architecture 有权
标题翻译：高性能存储器接口电路架构
公开(公告)号：US08305121B1
公开(公告)日：2012-11-06
申请号：US13168499
申请日：2011-06-24
申请人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
发明人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , H03L7/0805
摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
摘要翻译：可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略相移控制设置，以产生精细的相移控制设置。粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

55. 发明授权

US08217678B1 Fracturable lookup table and logic element 有权
标题翻译：可破坏的查找表和逻辑元素
公开(公告)号：US08217678B1
公开(公告)日：2012-07-10
申请号：US12834404
申请日：2010-07-12
申请人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy L. Lee
发明人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy L. Lee
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.
摘要翻译：逻辑元件包括存储器元件，多路复用器和控制器。多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级多路复用器和至少一个输出。控制器连接到多路复用器。在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出，第一级多路复用器。

56. 发明授权

US08188781B1 Memory interface phase-shift circuitry to support multiple frequency ranges 有权
标题翻译：存储器接口相移电路，以支持多个频率范围
公开(公告)号：US08188781B1
公开(公告)日：2012-05-29
申请号：US11531263
申请日：2006-09-12
申请人： Andy L. Lee
发明人： Andy L. Lee
IPC分类号： H03H11/26
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/222 , G11C11/4076 , G11C11/4096 , H03K2005/00058
摘要： The present invention provides a phase shift circuit that supports multiple frequency ranges. The phase shift circuit receives a plurality of control bits and causes a phase shift in a received signal, the phase shift corresponding to a number of time steps, the number depending on the control bits, and the time step is selected from a plurality of different time steps based on a frequency range associated with the received signal.
摘要翻译：本发明提供一种支持多个频率范围的相移电路。相移电路接收多个控制位，并且在接收信号中产生相移，对应于时间步数的相移，取决于控制位的数量，并且时间步长是从多个不同的基于与接收信号相关联的频率范围的时间步长。

57. 发明申请

US20120039142A1 SCALEABLE LOOK-UP TABLE BASED MEMORY 有权
标题翻译：可扩展的基于表的记忆
公开(公告)号：US20120039142A1
公开(公告)日：2012-02-16
申请号：US13277871
申请日：2011-10-20
申请人： Philip Pan , Andy L. Lee , Lu Zhou , Aniket Kadkol
发明人： Philip Pan , Andy L. Lee , Lu Zhou , Aniket Kadkol
IPC分类号： G11C7/12 , G11C5/14
CPC分类号： G11C11/418 , G11C7/00 , G11C7/1045 , G11C7/1048 , G11C7/12 , G11C7/22 , G11C8/10 , G11C11/4094 , G11C11/413 , G11C11/419 , G11C29/12 , G11C2029/0409 , G11C2029/1204 , G11C2029/2602
摘要： An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.
摘要翻译：提供一种集成电路，其具有包括可转换地用作配置随机存取存储器（CRAM）或静态随机存取存储器（SRAM））的存储元件阵列的逻辑元件。逻辑元件包括具有专用复用器的第一和第二对数据路径。在一个实施例中，第一和第二对数据路径被复用到阵列行的位线。逻辑元件还包括数据路径控制块，其产生用于每个专用多路复用器的控制信号。控制信号确定存储元件是否用作CRAM或SRAM。提供了一种用于在CRAM模式和SRAM模式之间选择性地配置存储器阵列的方法。

58. 发明授权

US08030962B2 Configuration random access memory 有权
标题翻译：配置随机存取存储器
公开(公告)号：US08030962B2
公开(公告)日：2011-10-04
申请号：US12868575
申请日：2010-08-25
申请人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
发明人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译：提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。每个存储器元件具有存储该存储器元件的数据的电容器。一对交叉耦合的反相器连接到电容器。逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。每个配置随机存取存储器元件可以具有透明晶体管。电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。逆变器可以用升高的电源电压供电。

59. 发明授权

US07969215B1 High-performance memory interface circuit architecture 有权
标题翻译：高性能存储器接口电路架构
公开(公告)号：US07969215B1
公开(公告)日：2011-06-28
申请号：US12467681
申请日：2009-05-18
申请人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
发明人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , H03L7/0805
摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
摘要翻译：可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略相移控制设置，以产生精细的相移控制设置。粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

60. 发明授权

US07911240B1 Clock switch-over circuits and methods 有权
标题翻译：时钟切换电路和方法
公开(公告)号：US07911240B1
公开(公告)日：2011-03-22
申请号：US11750293
申请日：2007-05-17
申请人： Gary Lai , Andy L. Lee , Ryan Fung , Vaughn Betz , Marcel A. LeBlanc
发明人： Gary Lai , Andy L. Lee , Ryan Fung , Vaughn Betz , Marcel A. LeBlanc
IPC分类号： G06F1/08
CPC分类号： G06F1/10
摘要： Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.
摘要翻译：时钟切换电路和方法为时钟路由网络提供时钟信号。根据一个实施例，多路复用器响应于从控制电路接收的开关选择信号在第一时钟信号和第二时钟信号之间进行选择。存储电路响应于多路复用器的输出时钟信号而存储使能信号。响应于来自存储电路的使能信号，逻辑电路将多路复用器的输出时钟信号传输到时钟路由网络。至少一个信号从时钟切换电路发送到控制电路。

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