会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 51. 发明授权
    • Dark field image reversal for gate or line patterning
    • 用于门或线图案的暗场图像反转
    • US06448164B1
    • 2002-09-10
    • US09716216
    • 2000-11-21
    • Christopher F. LyonsRamkumar SubramanianMarina V. PlatTodd P. Lukanc
    • Christopher F. LyonsRamkumar SubramanianMarina V. PlatTodd P. Lukanc
    • H01L213205
    • H01L21/0274H01L21/28123
    • A method of forming either a gate pattern or a line pattern in a resist by using a dark field mask and a combination of a negative photoresist and a positive photoresist. The dark field mask is used to create a hole within the positive photoresist, by exposing only a portion of the positive photoresist to light, and then by subjecting the positive photoresist to a developer. The negative photoresist is formed within the hole of the positive photoresist, and etched or polished so that it is only disposed within the hole. The negative photoresist and the positive photoresist are subjected to a flood light exposure, and then to a developer. This causes the positive photoresist to dissolve, leaving the negative photoresist, thereby providing a very-small-dimension resist pattern that can be used to form either a gate or a line for a semiconductor device.
    • 通过使用暗场掩模和负光致抗蚀剂和正性光致抗蚀剂的组合在抗蚀剂中形成栅极图案或线图案的方法。 暗场掩模用于在正性光致抗蚀剂中产生孔,通过仅将一部分正性光致抗蚀剂暴露于光,然后通过使正性光致抗蚀剂经受显影剂。 负光致抗蚀剂形成在正性光致抗蚀剂的孔内,并被蚀刻或抛光,使得其仅设置在孔内。 对负性光致抗蚀剂和正性光致抗蚀剂进行泛光曝光,然后进行显影。 这导致正性光致抗蚀剂溶解,留下负性光致抗蚀剂,从而提供可用于形成半导体器件的栅极或线的非常小的抗蚀剂图案。
    • 54. 发明授权
    • Gate pattern formation using a BARC as a hardmask
    • 使用BARC作为硬掩模的栅格图案形成
    • US6121123A
    • 2000-09-19
    • US924573
    • 1997-09-05
    • Christopher F. LyonsScott A. BellOlov Karlsson
    • Christopher F. LyonsScott A. BellOlov Karlsson
    • G03F7/09H01L21/027H01L21/28H01L21/3213H01L21/3205H01L21/4763
    • G03F7/091H01L21/0276H01L21/28123H01L21/32139Y10S438/952
    • A gate is formed on a semiconductor substrate by using a SiON film as both a bottom anti-reflective coating (BARC) and subsequently as a hardmask to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, and a SiON film over the conductive layer. The resist mask is formed on the SiON film. The SiON film improves the resist mask formation process and then serves as a hardmask during subsequent etching processes. Then the wafer stack is shaped to form one or more polysilicon gates by sequentially etching through selected portions of the SiON film and the gate conductive layer as defined by the etch windows in the original resist mask. Once the gate has been properly shaped, any remaining portions of either the resist mask or the SiON film are then removed.
    • 通过使用SiON膜作为底部抗反射涂层(BARC)并随后作为硬掩模在半导体衬底上形成栅极,以更好地控制通过深UV抗蚀剂掩模定义的栅极的临界尺寸(CD) 形成在其上。 晶片堆叠包括半导体衬底上的栅极氧化物层,栅极氧化物层上的多晶硅栅极层和导电层上的SiON膜。 在SiON膜上形成抗蚀剂掩模。 SiON膜改善了抗蚀剂掩模形成过程,然后在随后的蚀刻工艺中用作硬掩模。 然后通过依次蚀刻由原始抗蚀剂掩模中的蚀刻窗口所限定的SiON膜和栅极导电层的选定部分,将晶片堆叠成形以形成一个或多个多晶硅栅极。 一旦浇口已正确成型,然后除去抗蚀剂掩模或SiON膜的任何剩余部分。
    • 57. 发明授权
    • Gate pattern formation using a bottom anti-reflective coating
    • 使用底部抗反射涂层的栅格图案形成
    • US5963841A
    • 1999-10-05
    • US924370
    • 1997-09-05
    • Olov B. KarlssonChristopher F. LyonsMinh Van NgoScott A. BellDavid K. Foote
    • Olov B. KarlssonChristopher F. LyonsMinh Van NgoScott A. BellDavid K. Foote
    • H01L21/3213H01L21/302
    • H01L21/32139
    • A gate is formed on a semiconductor substrate by using a bottom anti-reflective coating (BARC) to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, a SiON BARC over the conductive layer, a thin oxide film over the SiON BARC. The resist mask is formed on the oxide film. The SiON BARC improves the resist mask formation process. The wafer stack is then shaped to form one or more polysilicon gates by sequentially etching through selected portions of the oxide film, the BARC, and the gate conductive layer as defined by the etch windows in the resist mask. Once properly shaped, the remaining portions of the resist mask, oxide film and SiON BARC are removed.
    • 通过使用底部抗反射涂层(BARC)在半导体衬底上形成栅极以更好地控制通过形成在其上的深UV抗蚀剂掩模所限定的栅极的临界尺寸(CD)。 晶片堆叠包括半导体衬底上的栅极氧化物层,栅极氧化物层上的多晶硅栅极层,导电层上的SiON BARC,SiON BARC上的薄氧化物膜。 在氧化物膜上形成抗蚀剂掩模。 SiON BARC改进了抗蚀剂掩模形成过程。 然后通过依次蚀刻通过抗蚀剂掩模中由蚀刻窗口限定的氧化膜,BARC和栅极导电层的选定部分,将晶片堆叠成形以形成一个或多个多晶硅栅极。 一旦适当成形,就去除了抗蚀剂掩模,氧化膜和SiON BARC的其余部分。