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    • 55. 发明授权
    • Thin film transistor array panel and liquid crystal display including the panel
    • 薄膜晶体管阵列面板和液晶显示器包括面板
    • US07294854B2
    • 2007-11-13
    • US10525039
    • 2002-09-18
    • Sang-Soo KimDong-Gyu Kim
    • Sang-Soo KimDong-Gyu Kim
    • H01L29/04H01L31/036H01L31/0376H01L31/20
    • H01L27/124G02F1/136213G02F1/136286H01L27/1255
    • A gate wire including a gate line extending in a transverse direction and a gate electrode connected to the gate line is form on an insulating substrate. A storage capacitor wire including a storage capacitor electrode line extending in the transverse direction and a storage electrode connected to the storage capacitor electrode line and located at the edges of a pixel area is formed. A semiconductor layer is formed on a gate insulating film covering the gate wire and the storage capacitor wire. A data wire is formed on the gate insulating film or the semiconductor layer and includes a data line intersecting the gate line to define the pixel area, a source electrode connected to the data line and located on the semiconductor layer, a drain electrode formed on the semiconductor layer and located opposite the source electrode with respect to the gate electrode, and a first storage capacitor conductor overlapping the storage capacitor electrode via the gate insulating film to form a storage capacitor. A pixel electrode electrically connected to the drain electrode and the first storage capacitor conductor is formed on the protective layer covering the data wire.
    • 包括在横向延伸的栅极线和连接到栅极线的栅电极的栅极线形成在绝缘基板上。 形成包括在横向延伸的辅助电容电极线和与辅助电容电极线连接并位于像素区域的边缘的存储电极的保持电容配线。 在覆盖栅极线和保持电容配线的栅极绝缘膜上形成半导体层。 数据线形成在栅极绝缘膜或半导体层上,并且包括与栅极线相交以限定像素区域的数据线,连接到数据线并位于半导体层上的源电极,形成在栅极绝缘膜上的漏电极 半导体层,并且相对于栅极位于与源电极相对的位置;以及第一存储电容器导体,经由栅极绝缘膜与存储电容电极重叠,形成存储电容。 电连接到漏电极和第一辅助电容导体的像素电极形成在覆盖数据线的保护层上。
    • 59. 发明授权
    • Thin film transistor array panel
    • 薄膜晶体管阵列面板
    • US07242451B2
    • 2007-07-10
    • US10523447
    • 2002-09-18
    • Dong-Gyu Kim
    • Dong-Gyu Kim
    • G02F1/1343
    • G02F1/133784G02F1/136209G02F1/136213G02F1/136227G02F1/136286G02F2001/13373G02F2001/136222G02F2201/40H01L27/1288
    • A thin film transistor array panel according to the present invention includes a first wire, a second wire, and a pixel electrode. The first wire is formed on an insulating substrate and is used as a gate line or a storage capacitor electrode. The second wire overlaps the first wire via a gate insulating layer and is used as a storage capacitor conductor or a drain electrode. The pixel electrode is formed on a passivation layer covering the second wire and is connected to the second wire through a contact hole of a second insulating layer. In order to secure aperture ratio of the pixel and to block light leakage, distances between the boundaries of the contact hole at the place where alignment treatment or rubbing ends and the boundaries of the first wire or the second wire adjacent thereto and located outside the boundaries of the contact hole are designed to be wider than those between the boundaries of the contact hole at the other places and the boundaries of the first wire or the second wire.
    • 根据本发明的薄膜晶体管阵列面板包括第一线,第二线和像素电极。 第一导线形成在绝缘基板上,用作栅极线或辅助电容电极。 第二导线经由栅极绝缘层与第一布线重叠,并用作存储电容器导体或漏电极。 像素电极形成在覆盖第二线的钝化层上,并通过第二绝缘层的接触孔连接到第二线。 为了确保像素的孔径比并阻止漏光,在对准处理或摩擦结束的地方的接触孔的边界与第一线或与其相邻并位于边界外侧的第二线的边界之间的距离 设计成比其他位置的接触孔的边界和第一线或第二线的边界之间的接触孔的宽度大。