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51. 发明申请

US20090172329A1 Providing secure services to a non-secure application 有权
标题翻译：为非安全应用程序提供安全服务
公开(公告)号：US20090172329A1
公开(公告)日：2009-07-02
申请号：US12003857
申请日：2008-01-02
申请人： Nigel Charles Paver , Stuart David Biles , Donald Felton
发明人： Nigel Charles Paver , Stuart David Biles , Donald Felton
IPC分类号： G06F12/14 , G06F9/46
CPC分类号： G06F21/74 , G06F12/1491 , G06F21/72
摘要： A data processing apparatus comprising a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor processing data in said non-secure mode; and a further processing device for performing a task in response to a request from said data processor issued from said non-secure mode, said task comprising processing data at least some of which is secure data, said further processing device comprising a secure data store, said secure data store not being accessible to processes running on said data processor in non-secure mode; wherein prior to issuing any of said requests said data processor is adapted to perform a set up operation on said further data processing device, said set up operation being performed by said data processor operating in said secure mode and comprising storing secure data in said secure data store on said further processing device, said secure data being secure data required by said further processing device to perform said task; wherein in response to receipt of said request from said data processor operating in said non-secure mode said further data processing device performs said task using data stored in said secure data store to access any secure data required.
摘要翻译：一种数据处理装置，包括用于以安全和非安全模式处理数据的数据处理器，所述数据处理器处理所述安全模式中的数据，以访问所述数据处理器不可访问的安全数据，所述数据处理器处理所述非安全模式; 以及另外的处理装置，用于响应于从所述非安全模式发出的来自所述数据处理器的请求执行任务，所述任务包括处理数据，其中至少一些是安全数据，所述另外的处理装置包括安全数据存储，所述安全数据存储器不能以非安全模式在所述数据处理器上运行的进程访问; 其中在发出任何所述请求之前，所述数据处理器适于对所述另外的数据处理设备执行建立操作，所述建立操作由所述数据处理器以所述安全模式操作并且包括将安全数据存储在所述安全数据中存储在所述另外的处理设备上，所述安全数据是所述另外的处理设备执行所述任务所需的安全数据; 其中响应于以所述非安全模式操作的所述数据处理器接收到所述请求，所述另外的数据处理设备使用存储在所述安全数据存储器中的数据来执行所述任务以访问所需的任何安全数据。

52. 发明申请

US20090138890A1 Contention management for a hardware transactional memory 审中-公开
公开(公告)号：US20090138890A1
公开(公告)日：2009-05-28
申请号：US12292565
申请日：2008-11-20
申请人： Geoffrey Blake , Trevor Nigel Mudge , Stuart David Biles , Nathan Yong Seng Chong , Emre Ozer , Ronald George Dreslinski
发明人： Geoffrey Blake , Trevor Nigel Mudge , Stuart David Biles , Nathan Yong Seng Chong , Emre Ozer , Ronald George Dreslinski
IPC分类号： G06F9/46
CPC分类号： G06F9/467 , G06F9/30087 , G06F9/466 , G06F12/084 , G06F12/0875 , G06F2212/452 , G06F2212/621
摘要： A hardware transactional memory 12, 14, 16, 18, 20 is provided within a multiprocessor 4, 6, 8, 10 system with coherency control and hardware transaction memory control circuitry 22 that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data 26, 28, 30. The conflict data characterises previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.

53. 发明申请

US20090133032A1 Contention management for a hardware transactional memory 有权
标题翻译：硬件事务内存的争用管理
公开(公告)号：US20090133032A1
公开(公告)日：2009-05-21
申请号：US12149003
申请日：2008-04-24
申请人： Stuart David Biles , Geoffrey Blake , Trevor Nigel Mudge
发明人： Stuart David Biles , Geoffrey Blake , Trevor Nigel Mudge
IPC分类号： G06F9/46
CPC分类号： G06F9/466 , G06F9/467 , G06F9/4881 , G06F9/528
摘要： A hardware transactional memory 12, 14, 16, 18, 20 is provided within a multiprocessor 4, 6, 8, 10 system with coherency control and hardware transaction memory control circuitry 22 that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data 26, 28, 30. The conflict data characterises previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.
摘要翻译：在具有相关性控制和硬件事务存储器控制电路22的多处理器4,6,8,10系统内提供硬件事务存储器12,14,16,18,20，其用于至少部分地根据处理事务的调度来管理在冲突数据26,28,30之间。冲突数据表征处理事务之前先前遇到的冲突。执行调度，使得如果冲突数据指示已经运行的处理事务中的一个先前与候选处理事务冲突，则候选处理事务将不被调度。

54. 发明授权

US07529889B2 Data processing apparatus and method for performing a cache lookup in an energy efficient manner 有权
标题翻译：用于以能量有效的方式执行高速缓存查找的数据处理装置和方法
公开(公告)号：US07529889B2
公开(公告)日：2009-05-05
申请号：US11503410
申请日：2006-08-14
申请人： Vladimir Vasekin , Stuart David Biles
发明人： Vladimir Vasekin , Stuart David Biles
IPC分类号： G06F12/08
CPC分类号： G06F12/0884 , G06F2212/1028 , Y02D10/13
摘要： A data processing apparatus and method are provided for performing a cache lookup in an energy efficient manner. The data processing apparatus has at least one processing unit for performing operations and a cache having a plurality of cache lines for storing data values for access by that at least one processing unit when performing those operations. The at least one processing unit provides a plurality of sources from which access requests are issued to the cache, and each access request, in addition to specifying an address, further includes a source identifier indicating the source of the access request. A storage element is provided for storing for each source an indication as to whether the last access request from that source resulted in a hit in the cache, and cache line identification logic determines, for each access request, whether that access request is seeking to access the same cache line as the last access request issued by that source. The cache control logic is operable when handling an access request to constrain the lookup procedure to only a subset of the storage blocks within the cache if it is determined that the access request is to the same cache line as the last access request issued by the relevant source, and the storage element indicates that the last access request from that source resulted in a hit in the cache. This yields significant energy savings when accessing the cache.
摘要翻译：提供了一种以能量效率方式执行高速缓存查找的数据处理装置和方法。所述数据处理装置具有用于执行操作的至少一个处理单元和具有多个高速缓存行的高速缓存，所述高速缓存行用于在执行所述操作时存储由所述至少一个处理单元访问的数据值。所述至少一个处理单元提供多个源，从所述多个源向所述高速缓存发出访问请求，并且除了指定地址之外，每个访问请求还包括指示所述访问请求的源的源标识符。提供存储元件，用于为每个源存储关于来自该源的最后访问请求是否导致高速缓存中的命中的指示，并且高速缓存行标识逻辑针对每个访问请求确定该访问请求是否正在寻求访问与该源发出的最后访问请求相同的高速缓存行。如果确定访问请求与由相关的最后访问请求发送到相同的高速缓存行，则处理访问请求以将查找过程限制为仅在缓存内的存储块的子集的情况下，高速缓存控制逻辑可操作源，并且存储元素指示来自该源的最后访问请求导致高速缓存中的命中。这在访问缓存时可以节省大量能源。

55. 发明申请

US20080270758A1 Multiple thread instruction fetch from different cache levels 有权
标题翻译：从不同的缓存级别获取多线程指令
公开(公告)号：US20080270758A1
公开(公告)日：2008-10-30
申请号：US11790811
申请日：2007-04-27
申请人： Emre Ozer , Stuart David Biles
发明人： Emre Ozer , Stuart David Biles
IPC分类号： G06F12/08 , G06F9/30
CPC分类号： G06F12/0811 , G06F9/3802 , G06F9/3851 , G06F12/0897
摘要： A data processing apparatus is provided wherein processing circuitry executes multiple program threads including at least one high priority thread and at least one lower priority thread. Instructions required by the threads are retrieved from a cache memory hierarchy comprising multiple cache levels. The cache memory hierarchy includes a bypass path for omitting a predetermined level of the cache memory hierarchy when performing a lookup procedure for a required instruction and for bypassing said predetermined level of the cache memory hierarchy when returning said required instruction to said processing circuitry. The bypass path is used by default when the requested instruction is for a lower priority thread.
摘要翻译：提供了一种数据处理装置，其中处理电路执行包括至少一个高优先级线程和至少一个较低优先级线程的多个程序线程。从包含多个高速缓存级别的缓存存储器层次中检索线程所需的指令。所述高速缓存存储器层级包括旁路路径，用于在执行所需指令的查找过程时省略所述高速缓存存储器层级的预定级别，以及当将所述所需指令返回给所述处理电路时绕过所述高速缓存存储器层级的所述预定级别。当请求的指令用于较低优先级的线程时，默认使用旁路路径。

56. 发明申请

US20080270749A1 Instruction issue control within a multi-threaded in-order superscalar processor 有权
标题翻译：多线程顺序超标量处理器中的指令问题控制
公开(公告)号：US20080270749A1
公开(公告)日：2008-10-30
申请号：US11790483
申请日：2007-04-25
申请人： Emre Ozer , Vladimir Vasekin , Stuart David Biles
发明人： Emre Ozer , Vladimir Vasekin , Stuart David Biles
IPC分类号： G06F15/00
CPC分类号： G06F9/3851 , G06F9/3822 , G06F9/3836 , G06F9/3838 , G06F9/384
摘要： A multi-threaded in-order superscalar processor 2 is described having a fetch stage 8 within which thread interleaving circuitry 36 interleaves instructions taken from different program threads to form an interleaved stream of instructions which is then decoded and subject to issue. Hint generation circuitry 62 within the fetch stage 8 adds hint data to the threads indicating that parallel issue of an associated instruction is permitted with one of more other instructions.
摘要翻译：描述了具有提取级8的多线程顺序超标量处理器2，线程交织电路36交织来自不同节目线程的指令，以形成交织的指令流，然后解码并发生问题。提取阶段8内的提示生成电路62向线程添加提示数据，指示相关指令的并行发行被许多其他指令之一允许。

57. 发明申请

US20070143515A1 Interrupt controller utilising programmable priority values 有权
标题翻译：中断控制器利用可编程优先级值
公开(公告)号：US20070143515A1
公开(公告)日：2007-06-21
申请号：US11603091
申请日：2006-11-22
申请人： Daniel Kershaw , Richard Roy Grisenthwaite , Stuart David Biles , David Hennah Mansell
发明人： Daniel Kershaw , Richard Roy Grisenthwaite , Stuart David Biles , David Hennah Mansell
IPC分类号： G06F13/26
CPC分类号： G06F21/52 , G06F13/26
摘要： An interrupt controller 2 is provided with priority registers 6 storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit 10 provides multiple mappings to the priority values stored in dependence upon the priority value manager 16, 18, seeking to make an access. In this way, a first priority value manager 18, such as a secure operating system, can be given exclusive access to the highest priority values whilst a second priority value manager 16, such as a non-secure operating system, can be given access to a range of priority values as stored which are of a lower priority and yet as written or read by the non-secure operating system appear to the non-secure operating system to have a different, such as higher, priority level.
摘要翻译：中断控制器2设置有优先级寄存器6，优先级寄存器6存储优先级值P 0 -P 9，用于确定接收到的中断信号I 0至I 9之间的优先级。优先级值访问电路10根据优先权值管理器16,18存储的优先权值提供多个映射，寻求进行访问。以这种方式，诸如安全操作系统的第一优先级值管理器18可以被授予对最高优先级值的排他访问，而可以给予诸如非安全操作系统的第二优先级值管理器16访问所存储的优先级较低的范围的优先权较低，但由非安全操作系统写入或读取，对于非安全操作系统来说，具有不同的，例如较高的优先级。

58. 发明授权

US09032188B2 Issue policy control within a multi-threaded in-order superscalar processor 有权
标题翻译：在多线程按顺序超标量处理器中发布策略控制
公开(公告)号：US09032188B2
公开(公告)日：2015-05-12
申请号：US12078100
申请日：2008-03-27
申请人： Emre Özer , Stuart David Biles
发明人： Emre Özer , Stuart David Biles
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38 , G06F9/48
CPC分类号： G06F9/3851 , G06F9/4881
摘要： A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2.
摘要翻译：多线程顺序超标量处理器2包括发行阶段12，其包括发行电路22,24，用于根据当前选择的发行策略来选择要发布到执行单元14,16的指令。多个不同的问题策略由相关联的不同策略电路28,30,32提供，并且策略电路28,30,32的这些实例中的哪一个被选择是由策略选择电路34根据检测到的动态行为的处理器2。

59. 发明授权

US08732523B2 Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus 有权
标题翻译：用于分析数据处理装置的存储元件内发生的瞬态故障的数据处理装置和方法
公开(公告)号：US08732523B2
公开(公告)日：2014-05-20
申请号：US13317593
申请日：2011-10-24
申请人： Emre Özer , Yiannakis Sazeides , Daniel Kershaw , Stuart David Biles
发明人： Emre Özer , Yiannakis Sazeides , Daniel Kershaw , Stuart David Biles
IPC分类号： G06F11/00
CPC分类号： G06F11/1415 , G06F11/0727 , G06F11/076 , G06F11/0787 , G06F2201/86
摘要： A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus.
摘要翻译：数据处理装置具有驻留在装置内的不同物理位置的多个存储元件，以及故障历史电路，用于检测每个存储元件中发生的局部瞬态故障，并且用于基于检测到的局部瞬态故障来维护全局瞬态故障历史数据。分析电路监视全局瞬态故障历史数据，以基于预定标准确定全局瞬态故障历史数据是否表示在数据处理装置内发生的随机瞬态故障，或指示协调的瞬时故障攻击。分析电路然后被配置为启动对协调的瞬态故障攻击的确定的对策动作。这提供了一种用于区分可能自然发生的随机瞬态故障的简单和有效的机制，以及可以在试图绕过数据处理设备的安全性时发起的协调的瞬态故障攻击。

60. 发明申请

US20140052921A1 STORE-EXCLUSIVE INSTRUCTION CONFLICT RESOLUTION 有权
标题翻译：存储专用指令冲突解决方案
公开(公告)号：US20140052921A1
公开(公告)日：2014-02-20
申请号：US14113723
申请日：2012-05-21
申请人： Stuart David Biles , Richard Roy Grisenthwaite , Bruce James Mathewson
发明人： Stuart David Biles , Richard Roy Grisenthwaite , Bruce James Mathewson
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F9/3004 , G06F9/3834 , G06F12/0815 , G06F12/0817
摘要： A data processing system includes a plurality of transaction masters (4, 6, 8, 10) each with an associated local cache memory (12, 14, 16, 18) and coupled to coherent interconnect circuitry (20). Monitoring circuitry (24) within the coherent interconnect circuitry (20) maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.
摘要翻译：数据处理系统包括多个具有相关本地高速缓存存储器（12,14,16,18）并且耦合到相干互连电路（20）的交易主机（4,6,8,10）。相干互连电路（20）内的监控电路（24）维护关于每个交易主机的状态变量（标志），以监视该交易主机的独占存储访问状态是否正在等待。当事务主机要执行存储专用指令时，将该事务主机的主体状态变量的当前值与设置独占存储访问时存储的该变量的先前值进行比较。如果存在匹配，则允许存储专用指令继续进行，并且具有挂起的独占存储访问状态的所有其他事务主器件的状态变量被改变。如果没有匹配，则专用指令的执行被标记为失败。

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