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51. 发明授权

US07902005B2 Method for fabricating a fin-shaped semiconductor structure and a fin-shaped semiconductor structure 有权
标题翻译：用于制造鳍状半导体结构和鳍状半导体结构的方法
公开(公告)号：US07902005B2
公开(公告)日：2011-03-08
申请号：US11934665
申请日：2007-11-02
申请人： Chris Stapelmann , Thomas Schulz
发明人： Chris Stapelmann , Thomas Schulz
IPC分类号： H01L21/00
CPC分类号： H01L29/66545 , H01L29/045 , H01L29/66795 , H01L29/7843 , H01L29/7845 , H01L29/785
摘要： A fin-shaped structure is formed from a semiconductor material. The fin-shaped structure is processed to generate a tensile strain within the semiconductor material along a longitudinal direction of the fin.
摘要翻译：鳍状结构由半导体材料形成。处理鳍状结构以沿着翅片的纵向方向在半导体材料内产生拉伸应变。

52. 发明申请

US20100123250A1 Feature Patterning Methods and Structures Thereof 有权
标题翻译：特征图案化方法及结构
公开(公告)号：US20100123250A1
公开(公告)日：2010-05-20
申请号：US12271606
申请日：2008-11-14
申请人： Thomas Schulz , Sergei Postnikov
发明人： Thomas Schulz , Sergei Postnikov
IPC分类号： H01L23/52 , H01L21/44
CPC分类号： H01L23/52 , H01L21/027 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.
摘要翻译：公开了图形特征的方法，制造半导体器件的方法和半导体器件。在一个实施例中，图案化特征的方法包括在第一材料层中形成特征的第一部分。特征的第二部分形成在第一材料层中，并且特征的第三部分形成在第二材料层中。

53. 发明授权

US07709827B2 Vertically integrated field-effect transistor having a nanostructure therein 失效
标题翻译：其中具有纳米结构的垂直集成的场效应晶体管
公开(公告)号：US07709827B2
公开(公告)日：2010-05-04
申请号：US10533550
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Richard Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Hönlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Johannes Richard Luyken , Wolfgang Rösner , Thomas Schulz , Michael Specht
IPC分类号： H01L21/8238
CPC分类号： H01L29/78642 , B82Y10/00 , H01L27/283 , H01L29/0673 , H01L29/0676 , H01L29/66439 , H01L29/66742 , H01L29/66787 , H01L29/775 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.
摘要翻译：本发明涉及垂直集成部件，部件布置和用于生产垂直集成部件的方法。垂直集成部件具有第一导电层，中间层，其部分地由第一导电层上的介电材料实现，中间层上的第二导电层和集成在中间层中的贯通保持件中的纳米结构。纳米结构的第一端部分耦合到第一导电层，第二端部分耦合到第二导电层。中间层包括在两个相邻的介电部分层之间的第三导电层，其厚度小于介电部分层中的至少一个的厚度。

54. 发明申请

US20100062573A1 METHOD FOR PRODUCING AN ELECTRONIC COMPONENT, METHOD FOR PRODUCING A THYRISTOR, METHOD FOR PRODUCING A DRAIN-EXTENDED MOS FILED-EFFECT TRANSISTOR, ELECTRONIC COMPONENT, DRAIN-EXTENDED MOS FIELD-EFFECT TRANSISTOR, ELECTRONIC COMPONENT ARRANGEMENT 有权
标题翻译：用于制造电子元件的方法，用于制造电容器的方法，用于产生漏极扩展MOS填充效应晶体管的方法，电子元件，漏极扩展的MOS场效应晶体管，电子元件布置
公开(公告)号：US20100062573A1
公开(公告)日：2010-03-11
申请号：US12620930
申请日：2009-11-18
申请人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
发明人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
IPC分类号： H01L21/332
CPC分类号： H01L29/78624 , H01L21/26586 , H01L21/84 , H01L27/0262 , H01L27/1203 , H01L29/66393 , H01L29/7436 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.
摘要翻译：在电子部件的制造方法中，在基板上或上方形成第一掺杂连接区域和第二掺杂连接区域，在所述第一掺杂连接区域和所述第二掺杂连接区域之间形成体区; 在身体区域上或上方形成彼此分离的至少两个栅极区域; 通过引入掺杂剂原子来掺杂体区的至少一个部分区域，其中通过形成在至少两个分开的栅极区域之间的至少一个中间区域将掺杂剂原子引入到体区的至少一个部分区域中。

55. 发明授权

US07488650B2 Method of forming trench-gate electrode for FinFET device 有权
标题翻译：形成FinFET器件的沟槽栅电极的方法
公开(公告)号：US07488650B2
公开(公告)日：2009-02-10
申请号：US11060959
申请日：2005-02-18
申请人： Thomas Schulz
发明人： Thomas Schulz
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66553 , H01L29/6656 , H01L29/66628 , H01L29/66795 , H01L29/78684 , H01L29/78687
摘要： A FinFET device having a trench-gate electrode, and a method of manufacture, is provided. The trench-gate electrode may be fabricated by forming a mask layer on a substrate having a semiconductor layer, e.g., silicon, formed thereon. A trench is formed in the mask layer and fins are formed in the exposed region of the underlying semiconductor layer. A gate electrode may be formed in the trench by, for example, depositing a gate electrode material such that the trench is filled, planarizing the surface to the surface of the mask layer, and optionally forming a recess in the surface of the gate electrode. Spacers may be formed in the trench and an optional gate dielectric layer may be formed over the fins prior to depositing the gate electrode material. Raised source and drain regions may be used by using selective epitaxial growth processes.
摘要翻译：提供了具有沟槽栅电极的FinFET器件及其制造方法。沟槽栅电极可以通过在其上形成有半导体层（例如硅）的衬底上形成掩模层来制造。在掩模层中形成沟槽，并且在下面的半导体层的暴露区域中形成翅片。可以通过例如沉积栅极电极材料形成栅电极，使得沟槽被填充，将表面平坦化到掩模层的表面，并且可选地在栅电极的表面中形成凹陷。可以在沟槽中形成间隔物，并且可以在沉积栅电极材料之前在鳍上方形成可选的栅极介电层。可以通过使用选择性外延生长工艺来使用升高的源极和漏极区。

56. 发明申请

US20080303096A1 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080303096A1
公开(公告)日：2008-12-11
申请号：US11810858
申请日：2007-06-07
申请人： Thomas Schulz
发明人： Thomas Schulz
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes forming a transistor, the transistor including a fin having a first side and a second side opposite the first side. The transistor includes a first gate electrode disposed on the first side of the fin and a second gate electrode disposed on the second side of the fin. The method includes forming a silicide or germanide of a metal on the first gate electrode and the second gate electrode of the transistor. The amount of the metal of the silicide or germanide is substantially homogeneous over the first gate electrode and the second gate electrode proximate the fin.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，制造半导体器件的方法包括形成晶体管，晶体管包括具有第一侧和与第一侧相对的第二侧的翅片。晶体管包括设置在鳍片的第一侧上的第一栅电极和设置在鳍片的第二侧上的第二栅电极。该方法包括在晶体管的第一栅电极和第二栅电极上形成金属的硅化物或锗化物。硅化物或锗化物的金属的量在靠近散热片的第一栅电极和第二栅电极上基本均匀。

57. 发明授权

US07454260B2 Systems and methods for production planning with sequence independent setup activities 有权
标题翻译：用于生产计划的系统和方法，具有无序独立设置活动
公开(公告)号：US07454260B2
公开(公告)日：2008-11-18
申请号：US11580090
申请日：2006-10-13
申请人： Hans-Juergen Biegler , Christian Embacher , Christoph Glania , Nikolaus Jacob , Thorsten Kulick , Thomas Schulz , Carmen Riepp
发明人： Hans-Juergen Biegler , Christian Embacher , Christoph Glania , Nikolaus Jacob , Thorsten Kulick , Thomas Schulz , Carmen Riepp
IPC分类号： G06F17/60
CPC分类号： G06Q10/06 , G06Q10/06316
摘要： Systems, methods, and computer program products are provided for planning production processes. In one implementation, a method is provided that includes the steps of planning a sequence of processes running on a resource, where the planning takes into account setup times for the resource for a process depending at least on predecessor process information, storing the sequence of processes, and defining time intervals for the resource within which setup times for processes are held constant independently of the predecessor process information.
摘要翻译：提供系统，方法和计算机程序产品用于规划生产过程。在一个实现中，提供了一种方法，其包括以下步骤：规划在资源上运行的进程序列，其中规划考虑至少基于先前过程信息的进程的资源的建立时间，存储进程序列并且定义用于进程的建立时间的资源的时间间隔，而与前一个进程信息无关。

58. 发明授权

US07416927B2 Method for producing an SOI field effect transistor 有权
标题翻译： SOI场效应晶体管的制造方法
公开(公告)号：US07416927B2
公开(公告)日：2008-08-26
申请号：US10948637
申请日：2004-09-23
申请人： Ralf Gottsche , Christian Pacha , Thomas Schulz , Werner Steinhogl
发明人： Ralf Gottsche , Christian Pacha , Thomas Schulz , Werner Steinhogl
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/78654 , H01L21/28123 , H01L29/6656 , H01L29/66772 , H01L29/66795 , H01L29/785 , H01L29/78642
摘要： Method for producing a first SOI field effect transistor with predetermined transistor properties by forming a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate, forming a spacer layer having a predetermined thickness, on at least a portion of the sidewalls of the laterally delimited layer sequence, and forming two source/drain regions having a predetermined dopant concentration profile, by introducing dopant into two surface regions of the substrate which are adjoined by the spacer layer, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions, wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by setting the dopant concentration profile.
摘要翻译：在具有预定晶体管性质的第一SOI场效应晶体管的制造方法中，通过在未掺杂的衬底上形成具有栅极绝缘层和栅极区域的横向限定的层序列，在至少一部分上形成具有预定厚度的间隔层横向限定的层序列的侧壁，并且通过将掺杂剂引入到由间隔层邻接的衬底的两个表面区域中，形成具有预定掺杂剂浓度分布的两个源极/漏极区域，层序列和间隔层形成防止掺杂剂被引入到两个源极/漏极区域之间的衬底的表面区域的阴影结构，其中通过设置间隔层的厚度并且通过设置掺杂剂来设定第一SOI场效应晶体管的预定晶体管特性浓度分布。

59. 发明申请

US20080116515A1 MUGFET WITH INCREASED THERMAL MASS 有权
标题翻译： MUGFET具有增加的热质量
公开(公告)号：US20080116515A1
公开(公告)日：2008-05-22
申请号：US11561170
申请日：2006-11-17
申请人： Harald Gossner , Christian Russ , Jens Schneider , Thomas Schulz
发明人： Harald Gossner , Christian Russ , Jens Schneider , Thomas Schulz
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L23/367 , H01L27/0248 , H01L29/66795 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at least in part of a material having a heat capacity equal to or larger than the heat capacity of the material of the source region, drain region and array of fins, the cooling elements being in close vicinity to fins of the array of fins electrically isolated from the fins of the array, the source region and the drain region. Other embodiments are also disclosed
摘要翻译：本文讨论的一些实施例包括具有源极区域，漏极区域和翅片阵列的半导体，其可操作地耦合到栅极区域，以控制流过源极区域和漏极区域之间的鳍片的电流。所述半导体还具有至少一部分形成有至少部分热容量等于或大于所述源极区域，漏极区域和散热片阵列的热容量的冷却元件的冷却元件，所述冷却元件处于闭合状态靠近与阵列的鳍片，源极区域和漏极区域电隔离的翅片阵列的翅片。还公开了其他实施例

60. 发明申请

US20080067587A1 Method for producing an electronic component, method for producing a thyristor, method for producing a drain-extended MOS filed-effect transistor, electronic component, drain-extended MOS field-effect transistor, electronic component arrangement 有权
标题翻译：电子元件的制造方法，晶闸管的制造方法，漏极扩展MOS场效应晶体管的制造方法，电子元件，漏极扩展MOS场效应晶体管，电子元件配置
公开(公告)号：US20080067587A1
公开(公告)日：2008-03-20
申请号：US11800984
申请日：2007-05-08
申请人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
发明人： Harald Gossner , Thomas Schulz , Christian Russ , Gerhard Knoblinger
IPC分类号： H01L29/78 , H01L21/332 , H01L21/336
CPC分类号： H01L29/78624 , H01L21/26586 , H01L21/84 , H01L27/0262 , H01L27/1203 , H01L29/66393 , H01L29/7436 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.
摘要翻译：在电子部件的制造方法中，在基板上或上方形成第一掺杂连接区域和第二掺杂连接区域，在所述第一掺杂连接区域和所述第二掺杂连接区域之间形成体区; 在身体区域上或上方形成彼此分离的至少两个栅极区域; 通过引入掺杂剂原子来掺杂体区的至少一个部分区域，其中通过形成在至少两个分开的栅极区域之间的至少一个中间区域将掺杂剂原子引入到体区的至少一个部分区域中。

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