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51. 发明申请

US20070198766A1 SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING A SEMICONDUCTOR MEMORY 失效
标题翻译：半导体存储器和制造半导体存储器的方法
公开(公告)号：US20070198766A1
公开(公告)日：2007-08-23
申请号：US11676847
申请日：2007-02-20
申请人： Makoto Mizukami , Shigeru Kinoshita , Shigeyuki Takagi
发明人： Makoto Mizukami , Shigeru Kinoshita , Shigeyuki Takagi
IPC分类号： G06F12/00
CPC分类号： H01L27/115 , G11C11/5628 , G11C16/0483 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory includes: a first memory cell transistor including: a first floating gate electrode provided on and insulated from the substrate; and a first control gate electrode provided on and insulated from the first floating gate electrode; and a second memory cell transistor including: a second floating gate electrode provided on and insulated from the substrate, an upper surface being larger than a lower surface, and the upper surface being lower than an upper surface of the first floating gate electrode; and a second control gate electrode provided on and insulated from the second floating gate electrode.
摘要翻译：半导体存储器包括：第一存储单元晶体管，包括：设置在基板上并与基板绝缘的第一浮栅; 以及设置在所述第一浮栅上并与所述第一浮栅绝缘的第一控制栅极; 以及第二存储单元晶体管，包括：设置在所述基板上并与所述基板绝缘的第二浮栅，上表面大于下表面，并且所述上表面低于所述第一浮栅电极的上表面; 以及设置在第二浮栅上并与第二浮栅电极绝缘的第二控制栅电极。

52. 发明授权

US08835934B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08835934B2
公开(公告)日：2014-09-16
申请号：US13414394
申请日：2012-03-07
申请人： Makoto Mizukami
发明人： Makoto Mizukami
IPC分类号： H01L29/78 , H01L29/47 , H01L29/161 , H01L29/16 , H01L27/098 , H01L27/07 , H01L29/10 , H01L29/417 , H01L29/06
CPC分类号： H01L27/0727 , H01L27/098 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/47 , H01L29/7806
摘要： A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a JFET region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench. The second conduction type second source region are formed in the first conduction type first source region. The trench-type source electrode is in contact with the first source region, the second source region, and the first conduction type semiconductor deposition layer to configure a Schottky junction.
摘要翻译：半导体器件包括第一导电型半导体衬底，第一导电型半导体淀积层，沟槽，第二导电型阱，JFET区，第一导电型第一源极区，第一源极区，沟槽型源电极栅极绝缘膜，栅电极和漏电极。沟槽基本上垂直于半导体淀积层形成，使得半导体沉积层暴露于沟槽的底部。第二导电类型的第二源极区域形成在第一导电型第一源极区域中。沟槽型源电极与第一源极区域，第二源极区域和第一导电型半导体沉积层接触以构成肖特基结。

53. 发明申请

US20120223333A1 SEMICONDUCTOR RECTIFIER DEVICE 有权
标题翻译：半导体整流器器件
公开(公告)号：US20120223333A1
公开(公告)日：2012-09-06
申请号：US13220107
申请日：2011-08-29
申请人： Makoto Mizukami
发明人： Makoto Mizukami
IPC分类号： H01L29/06 , H01L29/161
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0692 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/43 , H01L29/6606
摘要： A semiconductor rectifier device according to an embodiment includes a semiconductor substrate of a first conductive type of a wide gap semiconductor, a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm3 and 5E+16 atoms/cm3 inclusive, and a thickness thereof is 8 μm or more, a first semiconductor region of the first conductive type of the wide gap semiconductor formed on the semiconductor layer surface, a second semiconductor region of the second conductive type of the wide gap semiconductor formed as sandwiched by the first semiconductor regions, wherein a width of the second semiconductor region is 15 μm or more, a first electrode formed on the first and second semiconductor regions, and a second electrode formed on a lower surface of the semiconductor substrate.
摘要翻译：根据实施例的半导体整流器件包括宽半沟道半导体的第一导电类型的半导体衬底，形成在半导体衬底的上表面上的宽间隙半导体的第一导电类型的半导体层，其中杂质浓度的半导体层的厚度为8μm以上，形成在半导体层上的第一导电类型的宽间隙半导体的第一半导体区域形成为由所述第一半导体区域夹持的宽间隙半导体的第二导电类型的第二半导体区域，其中所述第二半导体区域的宽度为15μm以上，形成在所述第一半导体区域和所述第二半导体区域上的第一电极，以及形成在半导体基板的下表面上的第二电极。

54. 发明授权

US08183624B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08183624B2
公开(公告)日：2012-05-22
申请号：US12061075
申请日：2008-04-02
申请人： Makoto Mizukami , Kiyohito Nishihara
发明人： Makoto Mizukami , Kiyohito Nishihara
IPC分类号： H01L29/788
CPC分类号： H01L27/105 , H01L27/0688 , H01L27/11529 , H01L27/11531 , H01L27/11556
摘要： A semiconductor memory device includes a substrate having a step including a first upper surface and a second upper surface higher than the first upper surface, a memory cell array formed on the first upper surface, and a peripheral circuit formed on the second upper surface and configured to supply an electrical signal to the memory cell array. The memory cell array includes a stacked structure having a plurality of first interconnection layers and a plurality of second interconnection layers respectively connected to the first interconnection layers. The first interconnection layers are stacked on the first upper surface, are separated from each other by insulating films, and extend in a first direction. The second interconnection layers extend upward and are separated from each other by insulating films.
摘要翻译：半导体存储器件包括具有包括第一上表面和高于第一上表面的第二上表面的步骤的衬底，形成在第一上表面上的存储单元阵列和形成在第二上表面上的外围电路，以向存储单元阵列提供电信号。存储单元阵列包括具有分别连接到第一互连层的多个第一互连层和多个第二互连层的层叠结构。第一互连层堆叠在第一上表面上，通过绝缘膜彼此分离，并沿第一方向延伸。第二互连层向上延伸并通过绝缘膜彼此分离。

55. 发明授权

US08039886B2 Depletion-type NAND flash memory 有权
标题翻译：消耗型NAND闪存
公开(公告)号：US08039886B2
公开(公告)日：2011-10-18
申请号：US12603099
申请日：2009-10-21
申请人： Makoto Mizukami , Kiyohito Nishihara
发明人： Makoto Mizukami , Kiyohito Nishihara
IPC分类号： H01L29/94
CPC分类号： H01L27/11568 , G11C16/0483 , H01L21/84 , H01L27/11521 , H01L27/11524 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L27/1203
摘要： A depletion-type NAND flash memory includes a NAND string composed of a plurality of serially connected FETs, a control circuit which controls gate potentials of the plurality of FETs in a read operation, a particular potential storage, and an adjacent memory cell threshold storage, wherein each of the plurality of FETs is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer, the adjacent memory cell threshold storage stores a threshold of a source line side FET adjacent to a source line side of a selected FET, and the control circuit applies a potential to the gate electrode of the source line side FET in the read operation, the applied potential being obtained by adding a particular potential stored in the particular potential storage to a threshold stored in the adjacent memory cell threshold storage.
摘要翻译：耗尽型NAND闪存包括由多个串联连接的FET组成的NAND串，控制电路，其在读取操作中控制多个FET的栅极电位，特定的电位存储器和相邻的存储单元阈值存储器，其中，所述多个FET中的每一个是其阈值根据电荷累积层中的电荷量而变化的晶体管，所述相邻存储单元阈值存储器存储与所选择的FET的源极侧相邻的源极侧FET的阈值，并且控制电路在读取操作中向源极侧FET的栅电极施加电位，所施加的电位通过将存储在特定电位存储器中的特定电位加到存储在相邻存储单元阈值存储器中的阈值。

56. 发明授权

US07842564B2 Semiconductor memory device manufacturing method and semiconductor memory device 有权
标题翻译：半导体存储器件制造方法和半导体存储器件
公开(公告)号：US07842564B2
公开(公告)日：2010-11-30
申请号：US12167695
申请日：2008-07-03
申请人： Ichiro Mizushima , Hirokazu Ishida , Yoshio Ozawa , Takashi Suzuki , Fumiki Aiso , Makoto Mizukami
发明人： Ichiro Mizushima , Hirokazu Ishida , Yoshio Ozawa , Takashi Suzuki , Fumiki Aiso , Makoto Mizukami
IPC分类号： H01L21/84
CPC分类号： H01L27/11521 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/02667 , H01L21/7624 , H01L21/84 , H01L27/115 , H01L27/11524 , H01L27/11568 , H01L27/12 , H01L27/1203 , H01L29/66825
摘要： In a method of manufacturing a semiconductor memory device, an opening is made in a part of an insulating film formed on a silicon substrate. An amorphous silicon thin film is formed on the insulating film in which the opening has been made and inside the opening. Then, a monocrystal is solid-phase-grown in the amorphous silicon thin film, with the opening as a seed, thereby forming a monocrystalline silicon layer. Then, the monocrystalline silicon layer is heat-treated in an oxidizing atmosphere, thereby thinning the monocrystalline silicon layer and reducing the defect density. Then, a memory cell array is formed on the monocrystalline silicon layer which has been thinned and whose defect density has been reduced.
摘要翻译：在制造半导体存储器件的方法中，在形成于硅衬底上的绝缘膜的一部分上形成开口。在已经形成开口的绝缘膜和开口内部形成非晶硅薄膜。然后，将单晶在非晶硅薄膜中固相生长，以开口为种子，由此形成单晶硅层。然后，在氧化气氛中对单晶硅层进行热处理，从而使单晶硅层变薄并降低缺陷密度。然后，在已经变薄的缺陷密度降低的单晶硅层上形成存储单元阵列。

57. 发明授权

US07829948B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US07829948B2
公开(公告)日：2010-11-09
申请号：US11963046
申请日：2007-12-21
申请人： Fumitaka Arai , Ichiro Mizushima , Makoto Mizukami
发明人： Fumitaka Arai , Ichiro Mizushima , Makoto Mizukami
IPC分类号： H01L27/11
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11556 , H01L29/42348 , H01L29/792
摘要： A nonvolatile semiconductor memory according to an aspect of the invention comprises a semiconductor substrate which has an SOI region and an epitaxial region at its surface, a buried oxide film arranged on the semiconductor substrate in the SOI region, an SOI layer arranged on the buried oxide film, a plurality of memory cells arranged on the SOI layer, an epitaxial layer arranged in the epitaxial region, and a select gate transistor arranged on the epitaxial layer, wherein the SOI layer is made of a microcrystalline layer.
摘要翻译：根据本发明的一个方面的非易失性半导体存储器包括：在其表面具有SOI区域和外延区域的半导体衬底，设置在SOI区域中的半导体衬底上的掩埋氧化膜，布置在掩埋氧化物上的SOI层膜，布置在SOI层上的多个存储单元，布置在外延区中的外延层和布置在外延层上的选择栅极晶体管，其中SOI层由微晶层制成。

58. 发明申请

US20100187594A1 SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US20100187594A1
公开(公告)日：2010-07-29
申请号：US12710172
申请日：2010-02-22
申请人： Makoto Mizukami , Hideyuki Funaki
发明人： Makoto Mizukami , Hideyuki Funaki
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11556 , H01L27/11565 , H01L27/11568 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A semiconductor memory includes a semiconductor substrate, a buried insulating film formed on a part of an upper surface of the semiconductor substrate, and a semiconductor layer formed on another part of the upper surface of the semiconductor substrate. Each of the memory cell transistors comprises a first-conductivity-type source region, a first-conductivity-type drain region, and a first-conductivity-type channel region arranged in the semiconductor layer in the column direction, and a gate portion formed on a side surface of the channel region in the row direction.
摘要翻译：半导体存储器包括半导体衬底，形成在半导体衬底的上表面的一部分上的埋入绝缘膜和形成在半导体衬底的上表面的另一部分上的半导体层。每个存储单元晶体管包括在列方向上布置在半导体层中的第一导电类型源极区，第一导电型漏极区和第一导电类型沟道区，以及形成在沟道区域的行方向的侧面。

59. 发明授权

US07553728B2 Method of fabricating a non-volatile semiconductor memory 有权
标题翻译：制造非易失性半导体存储器的方法
公开(公告)号：US07553728B2
公开(公告)日：2009-06-30
申请号：US12206762
申请日：2008-09-09
申请人： Makoto Mizukami , Fumitaka Arai
发明人： Makoto Mizukami , Fumitaka Arai
IPC分类号： H01L21/336 , H01L27/108
CPC分类号： H01L27/115 , G11C16/0433 , G11C16/0483 , H01L27/11521 , H01L27/11524
摘要： An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors.
摘要翻译：具有多个存储单元晶体管的线性排列的非易失性半导体存储器包括：具有第一导电类型的第一半导体层; 第二半导体层，设置在所述第一半导体层上以防止杂质从所述第一半导体层扩散到所述第二半导体层上方的区域; 以及设置在所述第二半导体层上的第三半导体层，包括具有第二导电类型的第一源极区域，具有第二导电类型的第一漏极区域和具有用于每个存储单元晶体管的第二导电类型的第一沟道区域。

60. 发明申请

US20090014828A1 SEMICONDUCTOR MEMORY DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件制造方法和半导体存储器件
公开(公告)号：US20090014828A1
公开(公告)日：2009-01-15
申请号：US12167695
申请日：2008-07-03
申请人： Ichiro MIZUSHIMA , Hirokazu Ishida , Yoshio Ozawa , Takashi Suzuki , Fumiki Aiso , Makoto Mizukami
发明人： Ichiro MIZUSHIMA , Hirokazu Ishida , Yoshio Ozawa , Takashi Suzuki , Fumiki Aiso , Makoto Mizukami
IPC分类号： H01L29/06 , H01L21/36
CPC分类号： H01L27/11521 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/02667 , H01L21/7624 , H01L21/84 , H01L27/115 , H01L27/11524 , H01L27/11568 , H01L27/12 , H01L27/1203 , H01L29/66825
摘要： In a method of manufacturing a semiconductor memory device, an opening is made in a part of an insulating film formed on a silicon substrate. An amorphous silicon thin film is formed on the insulating film in which the opening has been made and inside the opening. Then, a monocrystal is solid-phase-grown in the amorphous silicon thin film, with the opening as a seed, thereby forming a monocrystalline silicon layer. Then, the monocrystalline silicon layer is heat-treated in an oxidizing atmosphere, thereby thinning the monocrystalline silicon layer and reducing the defect density. Then, a memory cell array is formed on the monocrystalline silicon layer which has been thinned and whose defect density has been reduced.
摘要翻译：在制造半导体存储器件的方法中，在形成于硅衬底上的绝缘膜的一部分上形成开口。在已经形成开口的绝缘膜和开口内部形成非晶硅薄膜。然后，将单晶在非晶硅薄膜中固相生长，以开口为种子，由此形成单晶硅层。然后，在氧化气氛中对单晶硅层进行热处理，从而使单晶硅层变薄并降低缺陷密度。然后，在已经变薄的缺陷密度降低的单晶硅层上形成存储单元阵列。

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