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51. 发明申请

US20070069293A1 Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby 有权
标题翻译：用于将体积衬底上的平面和非平面CMOS晶体管和由此制成的制品集成的工艺
公开(公告)号：US20070069293A1
公开(公告)日：2007-03-29
申请号：US11238444
申请日：2005-09-28
申请人： Jack Kavalieros , Justin Brask , Brian Doyle , Uday Shah , Suman Datta , Mark Doczy , Matthew Metz , Robert Chau
发明人： Jack Kavalieros , Justin Brask , Brian Doyle , Uday Shah , Suman Datta , Mark Doczy , Matthew Metz , Robert Chau
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L21/823828 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/1037 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
摘要翻译：一种能够将平面和非平面晶体管集成到体半导体衬底上的工艺，其中所有晶体管的沟道可以在连续的宽度范围内定义。

52. 发明申请

US20070063306A1 Multiple crystal orientations on the same substrate 审中-公开
标题翻译：在同一基底上的多个晶体取向
公开(公告)号：US20070063306A1
公开(公告)日：2007-03-22
申请号：US11234014
申请日：2005-09-22
申请人： Brian Doyle , Jack Kavalieros , Justin Brask , Suman Datta , Robert Chau
发明人： Brian Doyle , Jack Kavalieros , Justin Brask , Suman Datta , Robert Chau
IPC分类号： H01L27/095
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/02609 , H01L21/2022 , H01L21/823412 , H01L21/823481 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/785
摘要： Embodiments of the invention provide a substrate with a surface having different crystal orientations in different areas. Embodiments of the invention provide a substrate with a portion having a crystal orientation and another portion having a crystal orientation. N— and P-type devices may both be formed on the substrate, with each type of device having the proper crystal orientation for optimum performance.
摘要翻译：本发明的实施例提供一种具有在不同区域中具有不同晶体取向的表面的基底。本发明的实施方案提供了具有<100>晶体取向的部分和具有<110>晶体取向的另一部分的基底。可以在衬底上形成N型和P型器件，每种类型的器件具有适当的晶体取向以实现最佳性能。

53. 发明申请

US20070001173A1 Semiconductor device structures and methods of forming semiconductor structures 有权
标题翻译：半导体器件结构和形成半导体结构的方法
公开(公告)号：US20070001173A1
公开(公告)日：2007-01-04
申请号：US11158661
申请日：2005-06-21
申请人： Justin Brask , Jack Kavalieros , Uday Shah , Suman Datta , Amlan Majumdar , Robert Chau , Brian Doyle
发明人： Justin Brask , Jack Kavalieros , Uday Shah , Suman Datta , Amlan Majumdar , Robert Chau , Brian Doyle
IPC分类号： H01L29/10
CPC分类号： H01L29/7853 , H01L21/30608 , H01L21/30617 , H01L21/3085 , H01L21/84 , H01L29/04 , H01L29/045 , H01L29/0657 , H01L29/51 , H01L29/66795 , H01L29/78681 , H01L29/78684
摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
摘要翻译：对半导体膜的图案化方法进行说明。根据本发明的实施例，在具有全局晶体取向的硅膜上形成硬掩模材料，其中半导体膜具有第一晶面和第二晶面，其中第一晶面比第二晶面更致密并且其中所述硬掩模形成在所述第二晶体平面上。接下来，将硬掩模和半导体膜图案化成硬掩模覆盖的半导体结构。然后将覆盖有硬掩模的半导体半导体暴露于具有足够化学强度以蚀刻第二晶面但湿度不足以蚀刻第一晶体面的湿蚀刻工艺。

54. 发明申请

US20060292776A1 Strained field effect transistors 审中-公开
标题翻译：应变场效应晶体管
公开(公告)号：US20060292776A1
公开(公告)日：2006-12-28
申请号：US11167647
申请日：2005-06-27
申请人： Been-Yih Jin , Robert Chau , Suman Datta , Brian Doyle , Jack Kavalieros , Justin Brask , Mark Doczy , Matthew Metz , Markus Kuhn , Marko Radosavlievic , M. Shaheed , Patrick Keys
发明人： Been-Yih Jin , Robert Chau , Suman Datta , Brian Doyle , Jack Kavalieros , Justin Brask , Mark Doczy , Matthew Metz , Markus Kuhn , Marko Radosavlievic , M. Shaheed , Patrick Keys
IPC分类号： H01L21/8234 , H01L21/20 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L27/0922 , H01L29/1054 , H01L29/165 , H01L29/7848
摘要： An NMOS transistor may be formed with a biaxially strained silicon upper layer having a thickness of greater than 500 Angstroms. The resulting NMOS transistor may have good performance and may exhibit reduced self-heating. A PMOS transistor may be formed with both a biaxially and uniaxially strained silicon germanium layer. A source substrate bias applied to both NMOS and PMOS transistors can enhance their performance.
摘要翻译： NMOS晶体管可以形成为具有大于500埃的厚度的双轴应变硅上层。所得的NMOS晶体管可以具有良好的性能并且可以表现出减少的自热。 PMOS晶体管可以形成为双轴和单轴应变的硅锗层。施加到NMOS和PMOS晶体管的源极衬底偏置可以提高其性能。

55. 发明申请

US20060205167A1 Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress 有权
标题翻译：使用单轴压应力和双轴压应力的互补金属氧化物半导体集成电路
公开(公告)号：US20060205167A1
公开(公告)日：2006-09-14
申请号：US11078267
申请日：2005-03-11
申请人： Jack Kavalieros , Justin Brask , Mark Doczy , Matthew Metz , Suman Datta , Brian Doyle , Robert Chau , Everett Wang , Philippe Matagne , Lucian Shifren , Been Jin , Mark Stettler , Martin Giles
发明人： Jack Kavalieros , Justin Brask , Mark Doczy , Matthew Metz , Suman Datta , Brian Doyle , Robert Chau , Everett Wang , Philippe Matagne , Lucian Shifren , Been Jin , Mark Stettler , Martin Giles
IPC分类号： H01L21/336 , H01L21/44 , H01L21/8234
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/41783 , H01L29/66636 , H01L29/7834 , H01L29/7848 , Y10S438/933
摘要： A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.
摘要翻译：晶体管可以由不同层的硅锗形成，具有梯度锗浓度的最低层和具有恒定锗浓度的上层，使得最底层具有Si 1-x Ge Ge > x 。在PMOS侧，最高层可以是Si 1-y N y O y的形式。源极和漏极可以由PMOS侧的Si 1-z N z z z的外延硅锗形成。在一些实施例中，在PMOS器件中，x大于y且z大于x。因此，PMOS器件可以在通道方向上具有单轴压应力和面内双轴压应力。在某些情况下，应力的这种组合可能导致较高的移动性和增加的设备性能。

56. 发明授权

US07071064B2 U-gate transistors and methods of fabrication 失效
标题翻译： U型栅极晶体管及其制造方法
公开(公告)号：US07071064B2
公开(公告)日：2006-07-04
申请号：US10949994
申请日：2004-09-23
申请人： Brian Doyle , Surinder Singh , Uday Shah , Justin Brask , Robert Chau
发明人： Brian Doyle , Surinder Singh , Uday Shah , Justin Brask , Robert Chau
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/7853 , H01L29/66795
摘要： A process is described for manufacturing of non-planar multi-corner transistor structures. A fin of a semiconductor material having a mask on a top surface of the fin is formed on a first insulating layer. A second insulating layer is formed on the fin exposing a top surface of the mask, wherein a protection layer is deposited between the fin and the second insulating layer. Next, the mask is removed and spacers are formed on the fin adjacent to the protection layer. A recess having a bottom and opposing sidewalls is formed in the fin. A gate dielectric layer and a gate electrode are formed on the top surface, the opposing sidewalls of the fin and on the bottom and on the opposing sidewalls of the recess in the fin. A source region and a drain region are formed in the fin at the opposite sides of the gate electrode.
摘要翻译：描述了用于制造非平面多角晶体管结构的工艺。在第一绝缘层上形成具有在鳍的顶表面上的掩模的半导体材料的鳍。在翅片上形成第二绝缘层，露出掩模的顶表面，其中保护层沉积在散热片和第二绝缘层之间。接下来，去除掩模，并且在与保护层相邻的翅片上形成间隔物。在翅片中形成具有底部和相对侧壁的凹部。栅极电介质层和栅电极形成在翅片的顶表面，翅片的相对侧壁和底部上以及凹槽的相对侧壁上。源极区域和漏极区域形成在栅极的相对侧的鳍片中。

57. 发明申请

US20060138553A1 Nonplanar transistors with metal gate electrodes 有权
公开(公告)号：US20060138553A1
公开(公告)日：2006-06-29
申请号：US11362453
申请日：2006-02-24
申请人： Justin Brask , Brian Doyle , Jack Kavalleros , Mark Doczy , Uday Shah , Robert Chau
发明人： Justin Brask , Brian Doyle , Jack Kavalleros , Mark Doczy , Uday Shah , Robert Chau
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/41791 , H01L29/66439 , H01L29/66545 , H01L29/66795 , Y10S438/926 , Y10S438/974
摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

58. 发明申请

US20060080198A1 CASH TRANSACTION SYSTEM 审中-公开
标题翻译：现金交易系统
公开(公告)号：US20060080198A1
公开(公告)日：2006-04-13
申请号：US11161242
申请日：2005-07-27
申请人： Brian Doyle
发明人： Brian Doyle
IPC分类号： G06Q40/00
CPC分类号： G06Q20/04 , G06Q20/10 , G06Q20/385 , G06Q30/06 , G06Q40/00
摘要： A cash avoidance system uses an identifier associated with a hardware token such as a card to establish an account. Change from cash transactions are credited to the account to be spent for future purchases anonymously. The person in possession of the card may then debit the account to purchase goods and services. The transactions may be carried out over a mesh network.
摘要翻译：现金回收系统使用与硬币令牌（例如卡）相关联的标识符来建立帐户。从现金交易的变化记入未来以匿名方式购买的账户。拥有该卡的人可以借记帐户购买商品和服务。这些事务可以通过网状网络进行。

59. 发明申请

US20060030104A1 Integrating n-type and p-type metal gate transistors 有权
标题翻译：集成n型和p型金属栅晶体管
公开(公告)号：US20060030104A1
公开(公告)日：2006-02-09
申请号：US11248737
申请日：2005-10-11
申请人： Mark Doczy , Justin Brask , Steven Keating , Chris Barns , Brian Doyle , Michael McSwiney , Jack Kavalieros , John Barnak
发明人： Mark Doczy , Justin Brask , Steven Keating , Chris Barns , Brian Doyle , Michael McSwiney , Jack Kavalieros , John Barnak
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
摘要翻译：至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

60. 发明申请

US20060001109A1 High mobility tri-gate devices and methods of fabrication 失效
公开(公告)号：US20060001109A1
公开(公告)日：2006-01-05
申请号：US10883183
申请日：2004-06-30
申请人： Mohamad Shaheen , Brian Doyle , Suman Datta , Robert Chau , Peter Tolchinksy
发明人： Mohamad Shaheen , Brian Doyle , Suman Datta , Robert Chau , Peter Tolchinksy
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L29/785 , H01L21/76243 , H01L21/76254 , H01L21/76256 , H01L29/045 , H01L29/66772
摘要： A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.

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