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51. 发明授权

US07525319B1 Method and apparatus to electrically qualify high speed PCB connectors 有权
标题翻译：电连接高速PCB连接器的方法和装置
公开(公告)号：US07525319B1
公开(公告)日：2009-04-28
申请号：US12200208
申请日：2008-08-28
申请人： Rubina Firdaus Ahmed , Moises Cases , Bradley Donald Herrman , Kent Barclay Howieson , Bhyrav Murthy Mutnury , Pravin Patel , Peter Robert Seidel
发明人： Rubina Firdaus Ahmed , Moises Cases , Bradley Donald Herrman , Kent Barclay Howieson , Bhyrav Murthy Mutnury , Pravin Patel , Peter Robert Seidel
IPC分类号： G01R31/04 , G01R31/02 , G01R31/28
CPC分类号： G01R31/046
摘要： A method of electrically qualifying high speed printed circuit board (PCB) connectors includes mounting a PCB connector on a test card, sending bit patterns through a first portion of the test card, evaluating a waveform on a sense signal on a second portion of the test card for the bit patterns launched on said first portion of the test card to measure common mode noise, and comparing the measured common mode noise of the second portion of the test card to a golden standard performed on a pre-qualified connector. The first portion of the test card comprises connectors to inject bit patterns. The second portion of the test card includes a split plane which induces common mode noise on a sense signal, the sense signal, and a termination pack. If the measured common mode noise on the PCB connector is worse than the golden standard, then the PCB connector is disqualified. If the measured common mode noise on the PCB connector is as good as or better than the golden standard, then the PCB connector is qualified. A first section of the PCB connector connects to the first portion of the test card and a second section of the PCB connector connects to the second portion of the test card. Transmission lines in the test card and the sense line are tightly coupled by shortening a distance between the sense line and the transmission lines.
摘要翻译：电气限定高速印刷电路板（PCB）连接器的方法包括将PCB连接器安装在测试卡上，通过测试卡的第一部分发送位模式，在测试的第二部分上评估感测信号上的波形在测试卡的所述第一部分上发射的位模式的卡用于测量共模噪声，以及将测试卡的第二部分的测量的共模噪声与在预先标定的连接器上执行的黄金标准进行比较。测试卡的第一部分包括用于注入位模式的连接器。测试卡的第二部分包括在感测信号，感测信号和终端包上引起共模噪声的分离平面。如果PCB连接器上测得的共模噪声比黄金标准差，则PCB连接器不合格。如果PCB连接器上测得的共模噪声与黄金标准一样好或更好，则PCB连接器是合格的。 PCB连接器的第一部分连接到测试卡的第一部分，并且PCB连接器的第二部分连接到测试卡的第二部分。通过缩短感测线和传输线之间的距离，测试卡和感测线中的传输线紧密耦合。

52. 发明申请

US20090102487A1 Method for Validating Printed Circuit Board Materials for High Speed Applications 失效
标题翻译：用于验证高速应用的印刷电路板材料的方法
公开(公告)号：US20090102487A1
公开(公告)日：2009-04-23
申请号：US11875001
申请日：2007-10-19
申请人： Moises Cases , Bradley Donald Herrman , Kent Barclay Howieson , Erdem Matoglu , Bhyrav Murthy Mutnury , Pravin Patel , Nam Huu Pham , Celeb James Wesley
发明人： Moises Cases , Bradley Donald Herrman , Kent Barclay Howieson , Erdem Matoglu , Bhyrav Murthy Mutnury , Pravin Patel , Nam Huu Pham , Celeb James Wesley
IPC分类号： G01R31/02 , G01K3/00 , G01N25/72
CPC分类号： G01N25/72 , G01J5/0096 , G01R31/2818 , G01R31/2837 , G01R31/309
摘要： A method for testing a printed circuit board to determining the dielectric loss associated with the circuit board material relative to a standard. Dielectric losses in the material generate heat when a high frequency electronic signal, such as a microwave frequency signal, is communicated through a microstrip that is embedded within the printed circuit board. The temperature or spectrum at the surface of printed circuit board is measured and compared against the temperature or spectrum of the standard to determine whether the material under test is acceptable. While various temperature measurement devices may be used, the temperature is preferably measured without contacting the surface, such as using an infrared radiation probe.
摘要翻译：一种用于测试印刷电路板以确定与电路板材料相关的介电损耗相对于标准的方法。当诸如微波频率信号的高频电子信号通过嵌入在印刷电路板内的微带传输时，材料中的介电损耗产生热量。测量印刷电路板表面的温度或光谱，并与标准品的温度或光谱进行比较，以确定被测材料是否可接受。尽管可以使用各种温度测量装置，但是优选地在不接触表面的情况下测量温度，例如使用红外辐射探针。

53. 发明申请

US20090021264A1 METHOD AND APPARATUS FOR REPEATABLE DRIVE STRENGTH ASSESSMENTS OF HIGH SPEED MEMORY DIMMS 有权
标题翻译：用于高速记忆体可重复驱动强度评估的方法和装置
公开(公告)号：US20090021264A1
公开(公告)日：2009-01-22
申请号：US11780505
申请日：2007-07-20
申请人： Moises Cases , Daniel N. de Araujo , Bradley D. Herrman , Erdem Matoglu , Bhyrav M. Mutnury , Pravin Patel , Nam H. Pham
发明人： Moises Cases , Daniel N. de Araujo , Bradley D. Herrman , Erdem Matoglu , Bhyrav M. Mutnury , Pravin Patel , Nam H. Pham
IPC分类号： G01R31/02 , G06F11/00
CPC分类号： G01R31/2815 , G01R31/304 , G11C29/02 , G11C29/022 , G11C29/56 , G11C2029/5602
摘要： The present invention assesses memory (DIMM) strength by calculating frequency content of a radiated field which is collected by an apparatus, such as a dipole antenna. Radiated field is created by accelerated charge, which is a function of the slew rate or DIMM strength. Radiated power is directly proportional to the frequency at which bits are driven. By separating the radiated field from the near field or stored field, the DIMM strength content is isolated from other functional DIMM issues, such as tRCD latency, refresh cycles, addressing mode, etc. By examining the radiated power, the disadvantages of the prior art, such as by probing the DIMM's contacts, are avoided.
摘要翻译：本发明通过计算由诸如偶极天线的装置收集的辐射场的频率内容来评估存储器（DIMM）强度。辐射场由加速电荷产生，这是压摆率或DIMM强度的函数。辐射功率与驱动位的频率成正比。通过将辐射场与近场或存储场分离，DIMM强度内容与其他功能性DIMM问题（例如tRCD延迟，刷新周期，寻址模式等）隔离。通过检查辐射功率，现有技术的缺点，例如通过探测DIMM的触点。

54. 发明申请

US20090007048A1 DESIGN STRUCTURE FOR A COMPUTER MEMORY SYSTEM WITH A SHARED MEMORY MODULE JUNCTION CONNECTOR 审中-公开
标题翻译：具有共享存储器模块连接器的计算机存储器系统的设计结构
公开(公告)号：US20090007048A1
公开(公告)日：2009-01-01
申请号：US12203335
申请日：2008-09-03
申请人： MOISES CASES , Martin J. Crippen , Daniel N. de Araujo , Bradley D. Herman , Erdem Matoglu , William R. Milani , Bhyrav M. Mutnury , Pravin Patel , Nam H. Pham
发明人： MOISES CASES , Martin J. Crippen , Daniel N. de Araujo , Bradley D. Herman , Erdem Matoglu , William R. Milani , Bhyrav M. Mutnury , Pravin Patel , Nam H. Pham
IPC分类号： G06F17/50
CPC分类号： H01R25/006
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory module system and DIMM connector is provided. A DIMM connector includes a plurality of DIMM sockets for receiving a corresponding plurality of DIMMs in a radially oriented, angularly spaced orientation. The DIMM sockets are connected in parallel at a memory module junction so that socket terminals of each DIMM socket are joined to the same relative terminal of all the other DIMM sockets along electronic pathways of substantially equal length. A memory controller selectively communicates with the DIMMs via the DIMM junction. By virtue of the improved topology, impedance within the DIMM connector may be better matched to minimize reflections and improve signal quality.
摘要翻译：提供了体现在用于设计，制造和/或测试存储器模块系统和DIMM连接器的机器可读存储介质中的设计结构。 DIMM连接器包括多个DIMM插座，用于以径向定向的，有角度间隔的方向接收相应的多个DIMM。 DIMM插槽在存储器模块连接处并联连接，使得每个DIMM插座的插座端子沿着基本相等长度的电子路径连接到所有其他DIMM插槽的相同相对端子。存储器控制器经由DIMM连接器选择性地与DIMM通信。凭借改进的拓扑结构，可以更好地匹配DIMM连接器内的阻抗以最小化反射并提高信号质量。

55. 发明申请

US20080188095A1 ELECTRONIC CONNECTOR FOR CONTROLLING PHASE RELATIONSHIP BETWEEN SIGNALS 审中-公开
标题翻译：用于控制信号之间的相位关系的电子连接器
公开(公告)号：US20080188095A1
公开(公告)日：2008-08-07
申请号：US11670015
申请日：2007-02-01
申请人： Robert Joseph Christopher , Pravin Patel , Tony Carl Sass
发明人： Robert Joseph Christopher , Pravin Patel , Tony Carl Sass
IPC分类号： H01R12/00
CPC分类号： H01R13/6477 , H01R13/6471 , H01R13/6474 , H05K1/024
摘要： Connector and methods of connector design and manufacture are disclosed for achieving a desired phase relationship between signals carried along conductors of different lengths, while maintaining a desired impedance of the conductors. In one embodiment, a PCB connector includes a first plurality of electronic terminals and a second plurality of electronic terminals disposed on a connector body. A substrate has a dielectric constant that varies with location within the substrate. A first electronic conductor follows a first pathway within the substrate to experience a first effective dielectric constant. A second electronic conductor follows a second pathway within the substrate to experience a second effective dielectric constant. The first electronic conductor is longer than the second electronic conductor and the first effective dielectric constant is less than the second effective dielectric constant, to at least reduce phase error between signals. By satisfying the relationship l1/l2=sqrt(ε2/ε1), a phase error may be avoided.
摘要翻译：公开连接器和连接器设计和制造的方法，用于在保持导体的期望阻抗的同时实现沿着不同长度的导体携带的信号之间的期望的相位关系。在一个实施例中，PCB连接器包括第一多个电子端子和设置在连接器主体上的第二多个电子端子。衬底具有随着衬底内的位置而变化的介电常数。第一电子导体遵循衬底内的第一路径以经历第一有效介电常数。第二电子导体遵循衬底内的第二路径以经历第二有效介电常数。第一电子导体比第二电子导体长，并且第一有效介电常数小于第二有效介电常数，以至少减小信号之间的相位误差。通过满足关系l 1/2/2 / sqrt（ε2 /ε1 1），相位误差可以避免。

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