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51. 发明申请

US20090197382A1 MULTI-GATED, HIGH-MOBILITY, DENSITY IMPROVED DEVICES 失效
标题翻译：多层，高移动，密度改进的设备
公开(公告)号：US20090197382A1
公开(公告)日：2009-08-06
申请号：US12023347
申请日：2008-01-31
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26546 , H01L21/26586 , H01L21/845 , H01L29/66803 , H01L29/785
摘要： Disclosed herein are embodiments of an improved method of forming p-type and n-type MUGFETs with high mobility crystalline planes in high-density, chevron-patterned, CMOS devices. Specifically, semiconductor fins are formed in a chevron layout oriented along the centerline of a wafer. Gates are formed adjacent to the semiconductor fins such that they are approximately perpendicular to the centerline. Then, masked implant sequences are performed, during which halo and/or source/drain dopants are implanted into the sidewalls of the semiconductor fins on one side of the chevron layout and then into the sidewalls of the semiconductor fins on the opposite side of the chevron layout. The implant direction used during these implant sequences is substantially orthogonal to the gates in order to avoid mask shadowing, which can obstruct dopant implantation when separation between the semiconductor fins in the chevron layout is scaled (i.e., when device density is increased).
摘要翻译：本文公开了在高密度，人字纹图案化的CMOS器件中形成具有高迁移率晶面的p型和n型MUGFET的改进方法的实施方案。具体地，半导体散热片形成为沿着晶片的中心线定向的人字形布局。门形成在半导体翅片附近，使得它们大致垂直于中心线。然后，进行掩蔽的植入序列，在此期间将卤素和/或源极/漏极掺杂剂注入到人字形布局的一侧上的半导体鳍片的侧壁中，然后进入人字纹相反侧的半导体鳍片的侧壁布局。在这些植入序列期间使用的植入方向基本上与栅极正交，以避免掩模阴影，当阴影布局中的半导体鳍片之间的间隔被缩放时（即，当器件密度增加时），这可能阻碍掺杂剂注入。

52. 发明授权

US07569897B2 Low-capacitance contact for long gate-length devices with small contacted pitch 有权
标题翻译：具有小接触间距的长栅极长度器件的低电容接触
公开(公告)号：US07569897B2
公开(公告)日：2009-08-04
申请号：US11767635
申请日：2007-06-25
申请人： Brent A. Anderson , Edward J. Nowak
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/823431 , H01L21/823456 , H01L27/088 , H01L27/0886 , H01L27/1211 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.
摘要翻译：公开了平面和非平面场效应晶体管（FET）结构和形成结构的方法。这些结构包括在源极/漏极桥两端连接的分段有源器件（例如，用于非平面晶体管的多个半导体鳍片或用于平面晶体管的多个半导体层部分）。在源极/漏极桥之间的分段有源器件上图案化栅电极，使得栅极电极在段之间（即，半导体鳍片或部分之间）具有减小的长度。源极/漏极接触器接地在源/漏极桥上，使得它们仅与具有减小的栅极长度的栅电极的那些部分相对。这些FET结构可以被配置为同时使晶体管的密度最大化，从而使漏极功率最小化，并且将源极/漏极触点和栅极导体之间的寄生电容保持在预定值以下，这取决于性能和密度要求。

53. 发明申请

US20090101978A1 FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：具有合并源/排水硅酸盐的FIN型场效应晶体管结构及形成结构的方法
公开(公告)号：US20090101978A1
公开(公告)日：2009-04-23
申请号：US11873521
申请日：2007-10-17
申请人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.
摘要翻译：这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的设计结构的实施例，其中多个散热片部分或完全由高导电材料（例如，金属硅化物）。以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

54. 发明申请

US20090065834A1 IMAGERS HAVING ELECTRICALLY ACTIVE OPTICAL ELEMENTS 有权
标题翻译：具有电动活性光学元件的图像
公开(公告)号：US20090065834A1
公开(公告)日：2009-03-12
申请号：US11850798
申请日：2007-09-06
申请人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L27/146
CPC分类号： H01L27/14636 , H01L27/14625
摘要： A CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical functions. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect.
摘要翻译：一种包括有源像素单元阵列的CMOS图像传感器。每个有源像素单元包括衬底; 形成在基板表面处或下方的光敏装置，用于响应于入射光收集电荷载体; 以及形成在光敏器件上方的一个或多个透光导线结构，所述一个或多个导电线结构位于光敏器件上方的光路中。形成的透光导线结构提供电和光学功能。通过根据像素配色方案调整导线层的厚度以过滤光，提供光学功能。或者，透光导线结构可以形成为提供光聚焦功能的微透镜结构。用于导线层的电气功能包括用作电容器板，电阻器或互连件。

55. 发明授权

US07498208B2 Chevron CMOS trigate structure 有权
标题翻译：雪佛龙CMOS触发结构
公开(公告)号：US07498208B2
公开(公告)日：2009-03-03
申请号：US11689549
申请日：2007-03-22
申请人： Brent A. Anderson , Edward J. Nowak
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/42384 , H01L29/785
摘要： Disclosed herein is a structure with two different type tri-gate MOSFETs formed on the same substrate. Each MOSFET comprises a fin with optimal mobility for the particular type of MOSFET. Due to the processes used to form fins with different crystalline orientations on the same substrate, one of the MOSFETs has a fin with a lower mobility top surface. To inhibit inversion of the top surface, this MOSFET has a gate dielectric layer with a thicker region on the top surface than it does on the opposing sidewall surfaces. Additionally, several techniques for forming the thicker region of the gate dielectric layer are also disclosed.
摘要翻译：这里公开了在同一衬底上形成有两个不同类型的三栅极MOSFET的结构。每个MOSFET包括对于特定类型的MOSFET具有最佳移动性的鳍。由于用于在相同衬底上形成具有不同结晶取向的鳍片的工艺，所以MOSFET中的一个具有具有较低迁移率顶表面的翅片。为了抑制顶表面的反转，该MOSFET具有栅极电介质层，在顶表面上具有比在相对侧壁表面上更厚的区域。此外，还公开了用于形成栅极电介质层的较厚区域的几种技术。

56. 发明申请

US20090020806A1 ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 有权
标题翻译：不对称场效应晶体管结构与方法
公开(公告)号：US20090020806A1
公开(公告)日：2009-01-22
申请号：US11778185
申请日：2007-07-16
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336 , H01L29/76
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
摘要翻译：公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供改进的驱动电流，电路延迟最小）。具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定电容值）。

57. 发明申请

US20080299711A1 DUAL WORK-FUNCTION SINGLE GATE STACK 有权
标题翻译：双功能单门机柜
公开(公告)号：US20080299711A1
公开(公告)日：2008-12-04
申请号：US12175528
申请日：2008-07-18
申请人： Brent A. Anderson , Edward J. Nowak
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/82385 , H01L21/84
摘要： Disclosed is a complementary CMOS device having a first FET with sidewall channels and a second FET with a planar channel. The first FET can be a p-FET and the second FET can be an n-FET or vice versa. The conductor used to form the gate electrodes of the different type FETs is different and is pre-selected to optimize performance. For example, a p-FET gate electrode material can have a work function near the valence band and an n-FET gate electrode material can have a work function near the conduction band. The first gate electrodes of the first FET are located adjacent to the sidewall channels and the second gate electrode of the second FET is located above the planar channel. However, the device structure is unique in that the second gate electrode extends laterally above the first FET and is electrically coupled to the first gate electrodes.
摘要翻译：公开了具有具有侧壁通道的第一FET和具有平面通道的第二FET的互补CMOS器件。第一个FET可以是p-FET，第二个FET可以是n-FET，反之亦然。用于形成不同类型FET的栅电极的导体是不同的，并且是预选的以优化性能。例如，p-FET栅极材料可以在价带附近具有功函数，并且n-FET栅电极材料可以在导带附近具有功函数。第一FET的第一栅电极位于与侧壁通道相邻并且第二FET的第二栅电极位于平面通道上方。然而，器件结构是唯一的，因为第二栅电极横向于第一FET上方延伸并且电耦合到第一栅电极。

58. 发明申请

US20080284021A1 Method for FEOL and BEOL Wiring 失效
标题翻译： FEOL和BEOL接线方法
公开(公告)号：US20080284021A1
公开(公告)日：2008-11-20
申请号：US11749898
申请日：2007-05-17
申请人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/76885 , H01L21/76843 , H01L21/76844 , H01L21/76867 , H01L21/76895 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension).
摘要翻译：一种用于形成适用于FEOL和BEOL半导体制造应用的亚光刻尺寸的导电结构的方法。该方法包括在衬底上形成含硅材料的形貌特征; 在地形特征上形成介电帽; 施加掩模结构以暴露所述地形特征的侧壁上的图案，所述暴露图案对应于要形成的导电结构; 在所述侧壁的暴露部分处沉积金属并在所述暴露的侧壁部分处形成一个或多个金属硅化物导电结构; 去除所述电介质盖层; 并去除含硅的地形特征。结果是形成一个或多个金属硅化物导体结构，其形成用于单个光刻定义的特征。在示例性实施例中，形成的金属硅化物导电结构具有高纵横比，例如从1：1至20：1（高度与宽度尺寸）。

59. 发明授权

US07449735B2 Dual work-function single gate stack 有权
标题翻译：双功能单门堆叠
公开(公告)号：US07449735B2
公开(公告)日：2008-11-11
申请号：US11548020
申请日：2006-10-10
申请人： Brent A. Anderson , Edward J. Nowak
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L29/76 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/82385 , H01L21/84
摘要： Disclosed is a complementary CMOS device having a first FET with sidewall channels and a second FET with a planar channel. The first FET can be a p-FET and the second FET can be an n-FET or vice versa. The conductor used to form the gate electrodes of the different type FETs is different and is pre-selected to optimize performance. For example, a p-FET gate electrode material can have a work function near the valence band and an n-FET gate electrode material can have a work function near the conduction band. The first gate electrodes of the first FET are located adjacent to the sidewall channels and the second gate electrode of the second FET is located above the planar channel. However, the device structure is unique in that the second gate electrode extends laterally above the first FET and is electrically coupled to the first gate electrodes.
摘要翻译：公开了具有具有侧壁通道的第一FET和具有平面通道的第二FET的互补CMOS器件。第一个FET可以是p-FET，第二个FET可以是n-FET，反之亦然。用于形成不同类型FET的栅电极的导体是不同的，并且是预选的以优化性能。例如，p-FET栅极材料可以在价带附近具有功函数，并且n-FET栅电极材料可以在导带附近具有功函数。第一FET的第一栅电极位于与侧壁通道相邻并且第二FET的第二栅电极位于平面通道上方。然而，器件结构是唯一的，因为第二栅电极横向于第一FET上方延伸并且电耦合到第一栅电极。

60. 发明申请

US20080185649A1 Substrate backgate for trigate FET 有权
标题翻译：基板背板用于触发FET
公开(公告)号：US20080185649A1
公开(公告)日：2008-08-07
申请号：US12099211
申请日：2008-04-08
申请人： Brent A. Anderson , Matthew J. Breitwisch , Edward J. Nowak
发明人： Brent A. Anderson , Matthew J. Breitwisch , Edward J. Nowak
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate. A trench isolation structure extending through the polysilicon layer to the insulator layer isolates current flowing through the polysilicon layer from other devices on the silicon substrate.
摘要翻译：公开了具有背栅的三栅场效应晶体管和形成晶体管的相关方法。具体地说，后门结合在翅片的下部。三栅结构形成在翅片上并与后门电隔离。背栅可用于控制FET的阈值电压。在一个实施例中，背栅极延伸到p型硅衬底中的n阱。与n阱的接触允许将电压施加到后门。在n阱和p衬底之间产生的二极管将流过n阱的电流与衬底上的其他器件隔离，使得后栅极可以被独立地偏置。在另一个实施例中，背栅极延伸到p型硅衬底上的绝缘体层上的n型多晶硅层。与n型多晶硅层的接触允许电压施加到后门。通过多晶硅层延伸到绝缘体层的沟槽隔离结构将流过多晶硅层的电流与硅衬底上的其它器件隔离。

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