专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US06566214B1 Method of making a semiconductor device by annealing a metal layer to form metal silicide and using the metal silicide as a hard mask to pattern a polysilicon layer 失效
标题翻译：通过退火金属层以形成金属硅化物并且使用金属硅化物作为硬掩模来制造半导体器件以图案化多晶硅层的方法
公开(公告)号：US06566214B1
公开(公告)日：2003-05-20
申请号：US10047036
申请日：2002-01-17
申请人： Christopher F. Lyons , Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat
发明人： Christopher F. Lyons , Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat
IPC分类号： H01L213213
CPC分类号： H01L21/28123
摘要： A method of making a semiconductor device is provided. A polysilicon layer is formed over a substrate and a metal layer is formed on the polysilicon layer. The metal layer and the polysilicon layer are annealed to form a metal silicide layer on the polysilicon layer. The metal silicide layer is patterned and the polysilicon layer is then patterned using the patterned metal silicide layer as a mask. The patterned metal silicide and polysilicon layers may be used as a gate electrode of a MOSFET.
摘要翻译：提供制造半导体器件的方法。在衬底上形成多晶硅层，并且在多晶硅层上形成金属层。退火金属层和多晶硅层，以在多晶硅层上形成金属硅化物层。图案化金属硅化物层，然后使用图案化的金属硅化物层作为掩模来对多晶硅层进行构图。图案化的金属硅化物和多晶硅层可以用作MOSFET的栅电极。

52. 发明授权

US06127089A Interconnect structure with low k dielectric materials and method of making the same with single and dual damascene techniques 有权
标题翻译：具有低k介电材料的互连结构和使用单镶嵌和双镶嵌技术制作相同的方法
公开(公告)号：US06127089A
公开(公告)日：2000-10-03
申请号：US143105
申请日：1998-08-28
申请人： Ramkumar Subramanian , Christopher F. Lyons , Uzodinma Okoroanyanwu
发明人： Ramkumar Subramanian , Christopher F. Lyons , Uzodinma Okoroanyanwu
IPC分类号： G03F7/075 , H01L21/311 , H01L21/768 , G03C1/76
CPC分类号： H01L21/7681 , H01L21/31144 , H01L21/76802 , H01L21/76807 , G03F7/075
摘要： A damascene structure and method of making the same in a low k dielectric material employs an imageable layer in which the damascene pattern is provided. The imageable layer is a convertible layer that upon exposure to the plasma etch that etches the low k dielectric material, converts the silicon-rich imageble layer into a mask layer containing silicon dioxide, for example. The low k dielectric material is protected from further etching by the mask thus created.
摘要翻译：一种镶嵌结构及其在低k电介质材料中的制造方法采用其中提供镶嵌图案的可成像层。可成像层是可转换层，其在暴露于蚀刻低k介电材料的等离子体蚀刻时，例如将富含硅的图像层转换成含有二氧化硅的掩模层。通过由此产生的掩模来保护低k电介质材料免于进一步蚀刻。

53. 发明授权

US06423650B1 Ultra-thin resist coating quality by increasing surface roughness of the substrate 有权
公开(公告)号：US06423650B1
公开(公告)日：2002-07-23
申请号：US09371715
申请日：1999-08-09
申请人： Marina V. Plat , Christopher F. Lyons , Michael K. Templeton , Bhanwar Singh
发明人： Marina V. Plat , Christopher F. Lyons , Michael K. Templeton , Bhanwar Singh
IPC分类号： H01L2131
摘要： In one embodiment, the present invention relates to a method of processing a semiconductor substrate, involving the steps of providing the semiconductor substrate having an upper surface; roughening the upper surface of the semiconductor substrate so that the upper surface of the semiconductor substrate has an Rtm of about 10 Å or more; and depositing an ultra-thin photoresist on the upper surface of the semiconductor substrate, the ultra-thin photoresist having a thickness of about 2,000 Å or less.

54. 发明授权

US06287959B1 Deep submicron metallization using deep UV photoresist 失效
标题翻译：深亚微米金属化使用深紫外光致抗蚀剂
公开(公告)号：US06287959B1
公开(公告)日：2001-09-11
申请号：US09065352
申请日：1998-04-23
申请人： Christopher F. Lyons , Bhanwar Singh
发明人： Christopher F. Lyons , Bhanwar Singh
IPC分类号： H01L214763
CPC分类号： H01L21/0276 , H01L21/31116 , H01L21/3144 , H01L21/76802 , Y10S438/952 , Y10S438/97
摘要： Reflection of incident optical radiation from a highly reflective metal layer (12), such as aluminum, copper or titanium, into a photoresist layer (16) is reduced by interposing a layer of silicon oxynitride (14) between the metal and photoresist layers. The silicon oxynitride layer (14) is pre-treated with an oxidizing plasma to deplete surface nitrogen and condition the silicon oxynitride layer (14) to be more compatible with deep ultraviolet photoresists. The silicon oxynitride layer (14) further serves as an etch stop in the formation of interconnect openings (40), such as vias, contacts and trenches. The interconnect opening (40) is filled with a second metallization layer to achieve multi-layer electrical interconnection.
摘要翻译：通过在金属和光致抗蚀剂层之间插入一层氮氧化硅（14），将来自诸如铝，铜或钛的高反射金属层（12）的入射光辐射反射到光致抗蚀剂层（16）中。氮氧化硅层（14）用氧化等离子体进行预处理以消除表面氮，并且使氮氧化硅层（14）与深紫外光致抗蚀剂更相容。氧氮化硅层（14）还用作形成互连开口（40）的蚀刻停止层，例如通路，触点和沟槽。互连开口（40）填充有第二金属化层以实现多层电互连。

55. 发明授权

US06836398B1 System and method of forming a passive layer by a CMP process 有权
标题翻译：通过CMP工艺形成钝化层的系统和方法
公开(公告)号：US06836398B1
公开(公告)日：2004-12-28
申请号：US10284769
申请日：2002-10-31
申请人： Ramkumar Subramanian , Jane V. Oglesby , Minh Van Ngo , Mark S. Chang , Sergey D. Lopatin , Angela T. Hui , Christopher F. Lyons , Patrick K. Cheung , Ashok M. Khathuria
发明人： Ramkumar Subramanian , Jane V. Oglesby , Minh Van Ngo , Mark S. Chang , Sergey D. Lopatin , Angela T. Hui , Christopher F. Lyons , Patrick K. Cheung , Ashok M. Khathuria
IPC分类号： H01G435
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L21/3212 , H01L27/285 , H01L28/75
摘要： The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.
摘要翻译：本发明提供了通过平坦化工艺有助于形成半导体器件的系统和方法。本发明利用通常在化学机械平面化（CMP）工艺中发生的凹陷效应。在半导体器件上进行还原CMP工艺以形成无源层，而不是执行第一CMP，随后进行沉积和第二CMP以形成钝化层。还原CMP方法利用包含在电极的盘区域中形成钝化层的还原化学物质的浆料。因此，钝化层与用于形成电极的还原CMP工艺结合形成。

56. 发明授权

US06737222B2 Dual damascene process utilizing a bi-layer imaging layer 有权
标题翻译：双镶嵌工艺利用双层成像层
公开(公告)号：US06737222B2
公开(公告)日：2004-05-18
申请号：US09884834
申请日：2001-06-19
申请人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Scott A. Bell
发明人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Scott A. Bell
IPC分类号： G03F700
CPC分类号： H01L21/76829 , G03F7/0035 , G03F7/095 , H01L21/0274 , H01L21/31144 , H01L21/76801 , H01L21/76802 , H01L21/76808 , H01L2221/1031
摘要： A method of utilizing a multilayer photoresist to form contact holes and/or conductors utilizing a dual damascene process includes utilizing layered photoresists. A contact in a conductive line can be formed in a single deposition step or in a two-stage deposition step. Image layers can remain as part of the interconnect structure or be removed by a polishing technique. The process can be utilized for any conductive structures provided above a substrate of an integrated circuit.
摘要翻译：利用多层光刻胶形成接触孔和/或使用双镶嵌工艺的导体的方法包括利用层状光致抗蚀剂。可以在单个沉积步骤中或在两级沉积步骤中形成导电线中的接触。图像层可以保留为互连结构的一部分，或者通过抛光技术去除。该方法可用于设置在集成电路的衬底上的任何导电结构。

57. 发明授权

US06686270B1 Dual damascene trench depth monitoring 失效
标题翻译：双镶嵌沟深度监测
公开(公告)号：US06686270B1
公开(公告)日：2004-02-03
申请号：US10212983
申请日：2002-08-05
申请人： Ramkumar Subramanian , Christopher F. Lyons
发明人： Ramkumar Subramanian , Christopher F. Lyons
IPC分类号： H01L214763
CPC分类号： H01L21/76807 , H01L21/76813 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of dual damascene processing, involving forming a plurality of via openings in the insulation structure containing a single layer of a dielectric material; and simultaneously (i) forming a plurality of trenches in the insulation structure, each trench positioned along the substantially straight line of a group of via openings, and (ii) monitoring the formation of trenches using a scatterometry system to determine trench depth, and terminating forming the trenches when a desired trench depth is attained.
摘要翻译：本发明的一个方面涉及一种双镶嵌加工方法，包括在绝缘结构中形成多个通孔，该绝缘结构包含单层电介质材料; 并且（i）在所述绝缘结构中形成多个沟槽，每个沟槽沿着一组通孔开口的基本直线定位，以及（ii）使用散射测量系统监测沟槽的形成以确定沟槽深度，并且终止当获得所需的沟槽深度时形成沟槽。

58. 发明授权

US06624642B1 Metal bridging monitor for etch and CMP endpoint detection 有权
标题翻译：用于蚀刻和CMP端点检测的金属桥接监视器
公开(公告)号：US06624642B1
公开(公告)日：2003-09-23
申请号：US10016252
申请日：2001-12-10
申请人： Christopher F. Lyons , Ramkumar Subramanian , Steven C. Avanzino
发明人： Christopher F. Lyons , Ramkumar Subramanian , Steven C. Avanzino
IPC分类号： G01R2700
CPC分类号： H01L21/3212 , H01L21/32051 , H01L21/32136 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.
摘要翻译：公开了一种包含半导体衬底的晶片，在半导体衬底上形成的至少一个金属层，以及至少一个嵌入在晶片中和晶片中的至少一个的电传感器，以促进金属层在其进行时的实时监测减色金属化工艺。该系统包含晶片，该晶片包括形成在半导体衬底上的至少一个金属层，与晶片接触的至少一个电传感器，其可操作以检测和传输与晶片相关的电活动;以及电测量站，可操作以处理电活动从电传感器检测和接收，用于实时监测减色金属化处理。

59. 发明授权

US07169711B1 Method of using carbon spacers for critical dimension (CD) reduction 失效
标题翻译：使用碳间隔物进行临界尺寸（CD）还原的方法
公开(公告)号：US07169711B1
公开(公告)日：2007-01-30
申请号：US10170984
申请日：2002-06-13
申请人： Christopher F. Lyons , Philip A. Fisher , Richard J. Huang , Cyrus E. Tabery
发明人： Christopher F. Lyons , Philip A. Fisher , Richard J. Huang , Cyrus E. Tabery
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337
摘要： A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposited carbon film to form spacers on lateral side walls of the aperture of the patterned photoresist layer, etching the substrate using the formed spacers and patterned photoresist layer as a pattern to form a trench having a second width, and removing the patterned photoresist layer and formed spacers using an oxidizing etch.
摘要翻译：使用碳间隔物进行临界尺寸减小的方法可以包括在基底上提供图案化的光致抗蚀剂层，其中图案化的光致抗蚀剂层具有第一宽度的孔，在光致抗蚀剂层上沉积碳膜并蚀刻沉积的碳膜以形成间隔物在图案化光致抗蚀剂层的孔的侧壁上，使用所形成的间隔物和图案化的光致抗蚀剂层作为图案蚀刻衬底，以形成具有第二宽度的沟槽，并使用氧化蚀刻去除图案化的光致抗蚀剂层和形成的间隔物。

60. 发明授权

US07112489B1 Negative resist or dry develop process for forming middle of line implant layer 有权
标题翻译：用于形成线植入层中间的负阻抗或干式显影工艺
公开(公告)号：US07112489B1
公开(公告)日：2006-09-26
申请号：US11004691
申请日：2004-12-03
申请人： Christopher F. Lyons , Anna Minvielle , Marina V. Plat
发明人： Christopher F. Lyons , Anna Minvielle , Marina V. Plat
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L27/115 , H01L21/26513 , H01L27/11521
摘要： A method of implanting a middle of line (MOL) implant layer of a flash memory device that does not require a descumming step is disclosed. In a first embodiment, the method includes depositing a negative tone resist over the MOL implant layer. Portions of the negative tone resist in and above a plurality of trenches are not exposed to optical radiation, while portions surrounding the plurality of trenches are exposed. The unexposed portions are developed out thereby leaving a bottom surface of each trench substantially free of a resist residue. Implants can be placed in the MOL implant layer without the need for a descumming step. In a second embodiment, a bi-layer resist is deposited on the MOL implant layer, wherein the bi-layer resist includes a silicon containing top layer and a bottom layer. The bi-layer resist is patterned to expose a portion of the bottom layer that resides in and above a plurality of trenches. The bottom layer is dry etch developed using oxygen plasma as the etchant, thereby leaving a bottom surface of each trench substantially free of a resist residue. Implants can be placed in the MOL implant layer without the need for a descumming step.
摘要翻译：公开了一种注入不需要除尘步骤的闪速存储器件的中间线（MOL）注入层的方法。在第一实施例中，该方法包括在MOL植入层上沉积负色调抗蚀剂。在多个沟槽中和上方的负色调抗蚀剂的部分不暴露于光辐射，而围绕多个沟槽的部分被暴露。未曝光部分显影出来，从而留下每个沟槽的底表面基本上没有抗蚀剂残留物。植入物可以放置在MOL植入层中，而不需要除去步骤。在第二实施例中，双层抗蚀剂沉积在MOL注入层上，其中双层抗蚀剂包括含硅顶层和底层。图案化双层抗蚀剂以暴露驻留在多个沟槽中和上方的底层的一部分。底层是使用氧等离子体作为蚀刻剂进行干法蚀刻，从而留下每个沟槽的底表面基本上没有抗蚀剂残留物。植入物可以放置在MOL植入层中，而不需要除去步骤。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式