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51. 发明授权

US4969148A Serial testing technique for embedded memories 失效
标题翻译：嵌入式存储器的串行测试技术
公开(公告)号：US4969148A
公开(公告)日：1990-11-06
申请号：US319979
申请日：1989-03-07
申请人： Benoit Nadeau-Dostie , Allan Silburt , Vinod K. Agarwal
发明人： Benoit Nadeau-Dostie , Allan Silburt , Vinod K. Agarwal
IPC分类号： G01R31/28 , G11C11/401 , G11C29/00 , G11C29/02 , G11C29/16 , G11C29/56
CPC分类号： G11C29/16
摘要： A testing circuit interfaces serially with the data path of an embedded memory circuit formed from at least one memory unit having separated data input and output lines and tandem addressing. Part of the testing circuit is a series of two-input multiplexer units which are adapted to be embedded on the same chip as the memory circuit. The outputs of the multiplexer units connect to a respective one of the data input lines of the memory circuit. Excepting the first bit position, a first input of each multiplexer unit is adapted to connect to the data output line of the adjacent bit position in the memory circuit. The second inputs of the multiplexer units are adapted to connect to the data bus of the chip. A further part of the testing circuit is a finite state machine which is adapted to connect to the first input of the multiplexer unit at the first bit position and to the data output line at the least bit position. During testing, the finite state machine actuates the multiplexer units to connect the first bits, and for each address outputs a series of test bits, shifts those bits through the addressed word by a series of read and write operations, and examines those bit after their passage through the addressed word for defects in the memory circuit at that address. The finite state machine may or may not be embedded on the same chip as the memory circuit.

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