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51. 发明授权

US07236008B1 Multiple size memories in a programmable logic device 有权
标题翻译：可编程逻辑器件中的多个大小的存储器
公开(公告)号：US07236008B1
公开(公告)日：2007-06-26
申请号：US11611122
申请日：2006-12-14
申请人： Richard G. Cliff , Srinivas T. Reddy , Andy L. Lee , David Lewis
发明人： Richard G. Cliff , Srinivas T. Reddy , Andy L. Lee , David Lewis
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/17728
摘要： Circuits, methods, and apparatus that provide integrated circuits having memories with multiple sizes. The memories may be dedicated embedded memories, or they may be distributed memories formed using memories or lookup tables in logic elements or other appropriate circuits. Configuration bits not needed by logic elements used for distributed memories can be used for data storage as well. These various memories may be combined or otherwise linked or chained together in different combinations to form larger memories of varying sizes.
摘要翻译：提供具有多种尺寸的存储器的集成电路的电路，方法和装置。存储器可以是专用的嵌入式存储器，或者它们可以是使用逻辑元件或其他适当电路中的存储器或查找表形成的分布式存储器。用于分布式存储器的逻辑元件不需要的配置位也可以用于数据存储。这些各种存储器可以以不同的组合组合或以其他方式链接或链接在一起以形成不同大小的较大存储器。

52. 发明授权

US06480028B2 Programmable logic device architectures with super-regions having logic regions and memory region 有权
标题翻译：具有逻辑区域和存储区域的超区域的可编程逻辑器件架构
公开(公告)号：US06480028B2
公开(公告)日：2002-11-12
申请号：US10062741
申请日：2002-02-01
申请人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pederson , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
发明人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pederson , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.
摘要翻译：可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。每个逻辑区域包括可编程逻辑的多个子区域。每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在更高长度的超超区域互连资源装置。

53. 发明授权

US06462577B1 Configurable memory structures in a programmable logic device 有权
标题翻译：可编程逻辑器件中的可配置存储器结构
公开(公告)号：US06462577B1
公开(公告)日：2002-10-08
申请号：US09761608
申请日：2001-01-16
申请人： Andy L. Lee , Christopher F. Lane , Srinivas T. Reddy , Brian D. Johnson , Ketan H. Zaveri , Mario Guzman , Quyen Doan
发明人： Andy L. Lee , Christopher F. Lane , Srinivas T. Reddy , Brian D. Johnson , Ketan H. Zaveri , Mario Guzman , Quyen Doan
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , G11C8/12 , H03K19/17728
摘要： A programmable logic device is provided in which logic array blocks (LABs) may be programmably configured for use as one of a variety of memory structures. The configurable memory structures may have separate read and write addresses, thereby making it possible to implement a variety of memory structures such as FIFO memory, ROM, RAM, and shift-registers.
摘要翻译：提供了一种可编程逻辑器件，其中可编程地将逻辑阵列块（LAB）配置为用作各种存储器结构之一。可配置的存储器结构可以具有单独的读和写地址，从而使得可以实现各种存储器结构，例如FIFO存储器，ROM，RAM和移位寄存器。

54. 发明授权

US06384625B1 Programmable logic devices with enhanced multiplexing capabilities 有权
标题翻译：具有增强复用功能的可编程逻辑器件
公开(公告)号：US06384625B1
公开(公告)日：2002-05-07
申请号：US09823603
申请日：2001-03-30
申请人： Andy L. Lee , Christopher F. Lane , Bruce B. Pedersen
发明人： Andy L. Lee , Christopher F. Lane , Bruce B. Pedersen
IPC分类号： G06F738
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17728
摘要： Programmable logic modules on a programmable logic device each include a four-input look-up table circuit which can be programmed to allow the logic module to produce an output signal which can be any of a plurality of logical combinations of four input signals applied to the logic module. In addition, each logic module is augmented with additional circuitry that allows the logic module to be alternatively operated as a dynamic four-to-one multiplexer.
摘要翻译：可编程逻辑器件上的可编程逻辑模块均包括四输入查找表电路，其可被编程以允许逻辑模块产生输出信号，输出信号可以是四个输入信号的多个逻辑组合中的任何一个，逻辑模块。此外，每个逻辑模块都增加了额外的电路，允许逻辑模块交替地作为动态四对一多路复用器操作。

55. 发明授权

US06215326B1 Programmable logic device architecture with super-regions having logic regions and a memory region 有权
标题翻译：具有逻辑区域和存储区域的超区域的可编程逻辑器件架构
公开(公告)号：US06215326B1
公开(公告)日：2001-04-10
申请号：US09266235
申请日：1999-03-10
申请人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
发明人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.
摘要翻译：可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。每个逻辑区域包括可编程逻辑的多个子区域。每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在较高长度的超超区域互连资源装置。

56. 发明授权

US6157210A Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits 失效
公开(公告)号：US6157210A
公开(公告)日：2000-12-05
申请号：US082867
申请日：1998-05-21
申请人： Ketan Zaveri , Christopher F. Lane , Srinivas T. Reddy , Andy L. Lee , Cameron R. McClintock , Bruce B. Pedersen
发明人： Ketan Zaveri , Christopher F. Lane , Srinivas T. Reddy , Andy L. Lee , Cameron R. McClintock , Bruce B. Pedersen
IPC分类号： G01R31/3185 , G06F7/38 , C01D1/32
CPC分类号： G01R31/318516
摘要： A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.

57. 发明授权

US6091258A Redundancy circuitry for logic circuits 有权
标题翻译：用于逻辑电路的冗余电路
公开(公告)号：US6091258A
公开(公告)日：2000-07-18
申请号：US433544
申请日：1999-11-03
申请人： Cameron McClintock , Andy L. Lee , Richard G. Cliff
发明人： Cameron McClintock , Andy L. Lee , Richard G. Cliff
IPC分类号： G06F11/20 , G11C29/00 , H03K19/177 , H03K19/003 , H03K19/173
CPC分类号： H03K19/17764 , G11C29/808 , H03K19/17728
摘要： Redundant circuitry for a logic circuit such as a programmable logic device is provided. The redundant circuitry allows the logic circuit to be repaired by replacing a defective logic area on the circuit with a redundant logic circuit. Rows and columns of logic areas may be logically remapped by row and column swapping. The logic circuit contains dynamic control circuitry for directing programming data to various logic areas on the circuit in an order defined by redundancy configuration data. Redundancy may be implemented using either fully or partially redundant logic areas. Logic areas may be swapped to remap a partially redundant logic area onto a logic area containing a defect. The defect may then be repaired using row or column swapping or shifting. A logic circuit containing folded rows of logic areas may be repaired by replacing a defective half-row with a redundant half-row.
摘要翻译：提供了诸如可编程逻辑器件之类的逻辑电路的冗余电路。冗余电路允许通过用冗余逻辑电路替换电路上的故障逻辑区域来修复逻辑电路。逻辑区域的行和列可以通过行和列交换逻辑地重新映射。逻辑电路包含动态控制电路，用于以由冗余配置数据定义的顺序将编程数据引导到电路上的各种逻辑区域。可以使用完全或部分冗余的逻辑区域实现冗余。可以交换逻辑区域以将部分冗余的逻辑区域重新映射到包含缺陷的逻辑区域。然后可以使用行或列交换或移位来修复缺陷。可以通过用冗余半行代替缺陷半行来修复包含折叠行的逻辑区域的逻辑电路。

58. 发明授权

US09501407B1 First-in-first-out memory with dual memory banks 有权
标题翻译：先进先出的双存储器存储器
公开(公告)号：US09501407B1
公开(公告)日：2016-11-22
申请号：US13235228
申请日：2011-09-16
申请人： Ray Ruey-Hsien Hu , Andy L. Lee , David Lewis , Tony Ngai , Haiming Yu , Hao-Yuan Howard Chou
发明人： Ray Ruey-Hsien Hu , Andy L. Lee , David Lewis , Tony Ngai , Haiming Yu , Hao-Yuan Howard Chou
IPC分类号： G06F12/06 , G06F13/16
CPC分类号： G06F12/0607 , G06F13/1689 , Y02D10/14
摘要： A first-in-first-out memory may have first and second memory banks. A write controller may write data into the first and second memory banks. In performing write operations, the write controller may determine whether to write the data into the first bank or the second bank by evaluating a first bank empty flag and a second bank empty flag. When transitioning between writing in the first bank and the second bank, the write controller may latch a write address value indicative of the last location at which valid data was written in a given bank. A read controller may read data from the first and second memory bank. The read controller may determine when to transition between reading in the first bank and reading in the second bank by comparing a current read address to the latched write address value.
摘要翻译：先入先出的存储器可以具有第一和第二存储体。写控制器可以将数据写入第一和第二存储体。在执行写入操作时，写入控制器可以通过评估第一存储体空标志和第二存储体空标志来确定是否将数据写入第一存储体或第二存储体。当在第一组和第二组中的写入之间转换时，写入控制器可以锁存指示在给定存储体中写入有效数据的最后位置的写入地址值。读取控制器可以从第一和第二存储体读取数据。读取控制器可以通过将当前读取地址与锁存的写入地址值进行比较来确定何时在第一存储区中的读取和第二存储区中的读取之间转换。

59. 发明授权

US08995175B1 Memory circuit with PMOS access transistors 有权
标题翻译：具有PMOS存取晶体管的存储电路
公开(公告)号：US08995175B1
公开(公告)日：2015-03-31
申请号：US13350575
申请日：2012-01-13
申请人： Jun Liu , Irfan Rahim , Yanzhong Xu , Andy L. Lee
发明人： Jun Liu , Irfan Rahim , Yanzhong Xu , Andy L. Lee
IPC分类号： G11C11/412 , G11C5/14
CPC分类号： G11C5/14 , G11C11/412 , G11C11/418
摘要： A memory circuit that includes a memory storage unit and access transistors coupled to the memory storage unit, where the access transistors include PMOS transistors, is described. In one implementation, the memory circuit further includes a bias clamp transistor coupled to the memory storage unit.
摘要翻译：描述了一种存储器电路，其包括存储器存储单元和耦合到存储器存储单元的存取晶体管，其中存取晶体管包括PMOS晶体管。在一个实现中，存储器电路还包括耦合到存储器存储单元的偏置钳位晶体管。

60. 发明授权

US08487651B2 Multiple data rate memory interface architecture 有权
公开(公告)号：US08487651B2
公开(公告)日：2013-07-16
申请号：US13176284
申请日：2011-07-05
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/173
CPC分类号： G11C7/10 , H03K19/17744
摘要： The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.

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