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51. 发明授权

US06356117B1 Asynchronously controlling data transfers within a circuit 有权
标题翻译：异步地控制电路内的数据传输
公开(公告)号：US06356117B1
公开(公告)日：2002-03-12
申请号：US09676428
申请日：2000-09-29
申请人： Ivan E. Sutherland , Scott M. Fairbanks , Josephus C. Ebergen
发明人： Ivan E. Sutherland , Scott M. Fairbanks , Josephus C. Ebergen
IPC分类号： H03K1900
CPC分类号： G06F7/00
摘要： One embodiment of the present invention provides a system for controlling asynchronous data transfers within a circuit. This system operates by monitoring a first voltage level on a first conductor that specifies whether a first stage of the circuit contains data. The system also monitors a second voltage level on a second conductor that specifies whether a second stage of the circuit contains data. Upon detecting that the first voltage level indicates that first stage contains data to be transmitted to the second stage, and that the second voltage level indicates that the second stage does not contain data, and is therefore available to receive data from the first stage, the system transfers the data from the first stage to the second stage. This is accomplished by generating a second stage latch signal to latch data into the second stage from the first stage. It also involves changing the first voltage level to indicate that the first stage no longer contains data, and changing the second voltage level to indicate that the second stage contains data.
摘要翻译：本发明的一个实施例提供一种用于控制电路内的异步数据传输的系统。该系统通过监视指定电路的第一级是否包含数据的第一导体上的第一电压电平来操作。该系统还监视第二导体上的第二电压电平，其指定电路的第二级是否包含数据。当检测到第一电压电平指示第一级包含要发送到第二级的数据，并且第二电压电平指示第二级不包含数据，并且因此可用于从第一级接收数据时，系统将数据从第一阶段转移到第二阶段。这是通过产生第二级锁存信号来实现的，以将数据从第一级锁存到第二级。它还包括改变第一电压电平以指示第一级不再包含数据，并且改变第二电压电平以指示第二级包含数据。

52. 发明授权

US06351261B1 System and method for a virtual reality system having a frame buffer that stores a plurality of view points that can be selected and viewed by the user 失效
标题翻译：具有存储可由用户选择和观看的多个视点的帧缓冲器的虚拟现实系统的系统和方法
公开(公告)号：US06351261B1
公开(公告)日：2002-02-26
申请号：US08114546
申请日：1993-08-31
申请人： Bruce A. Reichlen , Ivan E. Sutherland
发明人： Bruce A. Reichlen , Ivan E. Sutherland
IPC分类号： G06F1700
CPC分类号： G06F3/011
摘要： A computer video display system and method is disclosed. The computer video display system includes a frame buffer for storing a multiplicity of view points of a model to be displayed, a measurement device for measuring an aspect of the user's movement, a view point device for ascertaining a point of view of the model to be displayed in response to the measurement device, a computational device for modifying the view point according to a predefined algorithm, an access device for accessing the appropriate display information from the frame buffer, and a head mounted display for displaying the selected view point of the model. During operation, the measuring device, the view point device, and the computational device continuously update the view points of the model in response to movements of the user. In response thereto, the access device traverses the frame buffer and provides the updated display information to the head mounted display. The image, as seen through the head mounted display, appears to be continuous, fluid and natural.
摘要翻译：公开了一种计算机视频显示系统和方法。计算机视频显示系统包括用于存储要显示的模型的多个视点的帧缓冲器，用于测量用户移动方面的测量装置，用于确定模型的观点的视点装置响应于测量装置而显示的计算装置，用于根据预定义的算法修改视点的计算装置，用于从帧缓冲器访问适当的显示信息的访问装置以及用于显示模型的所选视点的头戴式显示器。在操作期间，测量装置，视点装置和计算装置响应于用户的移动持续地更新模型的视点。响应于此，访问设备遍历帧缓冲器并将更新的显示信息提供给头戴式显示器。通过头戴式显示器看到的图像似乎是连续的，流畅的和自然的。

53. 发明授权

US06304125B1 Method for generating and distribution of polyphase clock signals 有权
标题翻译：多相时钟信号的产生和分配方法
公开(公告)号：US06304125B1
公开(公告)日：2001-10-16
申请号：US09146815
申请日：1998-09-04
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： G06F104
CPC分类号： H03K5/15013
摘要： A method of generating and distributing clock signals is described. The method provides synchronous clock signals in as many phases as a designer of a given circuit finds useful. The method acknowledges timing constraints of the controlled system, and adjusts the clock phases appropriately to meet the needs of the local data circuits using the clock signals. The method uses stages of clock signal generators which are coupled to appropriate portions of the datapath and to each other for controlling the datapath and to provide information about clock signal timing to each other. By adding delay elements, the method can also be used to test the design of the given circuit.
摘要翻译：描述了一种产生和分配时钟信号的方法。该方法提供与给定电路的设计者有用的多个相位的同步时钟信号。该方法确认受控系统的时序约束，并且适当地调整时钟相位以满足使用时钟信号的本地数据电路的需要。该方法使用时钟信号发生器的级，其耦合到数据路径的适当部分并且彼此相连以控制数据路径并且提供关于时钟信号定时的信息。通过添加延迟元件，该方法也可以用于测试给定电路的设计。

54. 发明授权

US5805838A Fast arbiter with decision storage 失效
标题翻译：快速仲裁器与决策存储
公开(公告)号：US5805838A
公开(公告)日：1998-09-08
申请号：US655999
申请日：1996-05-31
申请人： Ivan E. Sutherland , Lee S. Tavrow
发明人： Ivan E. Sutherland , Lee S. Tavrow
IPC分类号： G06F12/00 , G06F9/48 , G06F13/364 , H01J13/00
CPC分类号： G06F13/364
摘要： Improved circuits for implementing various embodiments of high performance arbiters are disclosed. In one embodiment, a late-done arbiter is implemented by combining a late-decision arbiter with a decision storage (or queue) device. In another embodiment, an arbiter implementation that extends the amount of storage available for decisions is disclosed. A decision making device such as a simple arbiter is followed by a decision storage device such as a queue or a first in first out (FIFO) register of any number of stages. The decision storage device following the arbiter allows the arbiter to report each decision as quickly as it can and to start the next decision making cycle.
摘要翻译：公开了用于实现高性能仲裁器的各种实施例的改进电路。在一个实施例中，通过将后期决策仲裁器与决策存储（或队列）设备组合来实现后期完成的仲裁器。在另一个实施例中，公开了延长可用于决定的存储量的仲裁器实现。诸如简单仲裁器的决策设备之后是诸如队列或任何级数的先进先出（FIFO）寄存器的决策存储设备。遵循仲裁器的决策存储设备允许仲裁者尽可能快地报告每个决策，并开始下一个决策循环。

55. 发明授权

US5758139A Control chains for controlling data flow in interlocked data path circuits 失效
标题翻译：用于控制联锁数据路径电路中的数据流的控制链
公开(公告)号：US5758139A
公开(公告)日：1998-05-26
申请号：US636260
申请日：1996-04-23
申请人： Ivan E. Sutherland , Charles E. Molnar
发明人： Ivan E. Sutherland , Charles E. Molnar
IPC分类号： G11C7/00 , G06F5/06 , G06F5/08 , G06F9/38 , G06F13/00
CPC分类号： G06F5/08 , G06F9/3824 , G06F9/384 , G06F9/3842 , G06F9/3867
摘要： A technique is disclosed for interlocking FIFO data paths. The data paths are interlocked using a series of control elements which receive input signals not only from the other control elements of their own path, but also from control elements of an adjacent data path. Queues may also be employed between the FIFO control chains to provide greater freedom in the interlocking mechanism.
摘要翻译：公开了一种用于互锁FIFO数据路径的技术。数据路径使用一系列控制元件互锁，这些控制元件不仅从其自身路径的其他控制元件接收输入信号，而且从相邻数据路径的控制元件接收输入信号。也可以在FIFO控制链之间使用队列，以提供联锁机构的更大的自由度。

56. 发明授权

US5748539A Recursive multi-channel interface 失效
标题翻译：递归多通道接口
公开(公告)号：US5748539A
公开(公告)日：1998-05-05
申请号：US811909
申请日：1997-03-05
申请人： Robert F. Sproull , Ivan E. Sutherland
发明人： Robert F. Sproull , Ivan E. Sutherland
IPC分类号： G11C7/00 , G06F5/06
CPC分类号： G06F5/065
摘要： A multi-channel recursive interface having independent channels that can be used in, for example, multi-level memory systems is disclosed. Separate read and write command channels and read and write completion channels permit concurrent read and write operations. A memory system according to the present invention uses a write buffer to resolve read data ambiguity when concurrently reading and writing into the same memory location. With independent and asynchronous read and write channels, the interface of the present invention retains its properties even if separated from the system it interfaces by communication channels exhibiting any latency such as first in first out (FIFO) registers of arbitrary lengths. Such FIFOs can improve the throughput of the communication channels between the interface and the system it interfaces with. The recursive interface can flexibly serve many levels of memory.
摘要翻译：公开了一种具有可用于例如多级存储器系统的独立信道的多通道递归接口。单独的读写命令通道和读写完成通道允许并发读写操作。根据本发明的存储器系统在同时读取和写入相同存储器位置时使用写入缓冲器来解决读取数据模糊性。具有独立和异步的读写通道，本发明的接口即使与系统分离，也保持其特性，它通过展现任何长度的先入先出（FIFO）寄存器等任何延迟的通信通道进行接口。这样的FIFO可以提高接口与其接口的系统之间的通信信道的吞吐量。递归接口可以灵活地提供许多级别的内存。

57. 发明授权

US5713025A Asynchronous arbiter using multiple arbiter elements to enhance speed 失效
标题翻译：异步仲裁器使用多个仲裁器元素来提高速度
公开(公告)号：US5713025A
公开(公告)日：1998-01-27
申请号：US303247
申请日：1994-09-08
申请人： Charles E. Molnar , Ian W. Jones , Ivan E. Sutherland
发明人： Charles E. Molnar , Ian W. Jones , Ivan E. Sutherland
IPC分类号： G06F9/38 , G06F13/364 , H04L25/08 , G06F13/14
CPC分类号： G06F9/3824 , G06F13/364 , G06F9/384 , G06F9/3842 , G06F9/3867 , G06F9/3869 , H04L25/085
摘要： An arbiter circuit is described that is capable of granting a first user access to a shared resource while concurrently arbitrating subsequent requests from the first user to other users seeking access to the shared resource. The arbiter of the present invention includes a first arbiter element and a second arbiter element. The first arbiter element is initially used to arbitrate and issue a grant signal in response to one or more request signals from two or more users. The second arbiter element arbitrates and issues the next grant signal in response to subsequent request signal or signals from the one or other users. In one embodiment of the invention, the first and second arbiter elements are used alternately. In other embodiments, third and fourth arbiter elements are used to arbitrate in response to subsequent requests. The arbiter circuits of the present invention all reduce the delays in the access of users to the shared resource.
摘要翻译：描述了一种仲裁器电路，其能够授予第一用户对共享资源的访问，同时将来自第一用户的后续请求同时仲裁到寻求对共享资源的访问的其他用户。本发明的仲裁器包括第一仲裁器元件和第二仲裁器元件。第一仲裁器元件最初用于响应于来自两个或更多个用户的一个或多个请求信号仲裁并发出授权信号。第二仲裁器元件响应于来自一个或其他用户的后续请求信号而仲裁并发布下一授权信号。在本发明的一个实施例中，交替使用第一和第二仲裁器元件。在其他实施例中，第三和第四仲裁器元件用于响应于后续请求进行仲裁。本发明的仲裁器电路全部减少了用户访问共享资源的延迟。

58. 发明授权

US5684724A Flashback simulator 失效
标题翻译：闪回模拟器
公开(公告)号：US5684724A
公开(公告)日：1997-11-04
申请号：US521478
申请日：1995-08-30
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： G01R31/28 , G06F17/50 , G06F19/00 , G06Q50/00 , G06F9/455
CPC分类号： G06F17/5022
摘要： A simulator is described in which the simulator can flashback to simulate events that in simulated time actually occurred earlier than other events already simulated. The simulator removes the restriction of a monotonic relationship between simulation time and simulated time, enabling improved simulator performance.
摘要翻译：描述了一种模拟器，其中模拟器可以闪回以模拟在模拟时间中实际发生的事件早于已经模拟的其他事件。模拟器消除了模拟时间和模拟时间之间单调关系的限制，从而提高了模拟器性能。

59. 发明授权

US4900218A Robot arm structure 失效
标题翻译：机器人手臂结构
公开(公告)号：US4900218A
公开(公告)日：1990-02-13
申请号：US746222
申请日：1985-06-18
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： B25J18/06
CPC分类号： B25J18/06 , Y10T74/20323
摘要： Disclosed is a flexible robot arm structure utilizing an elongate skeletal frame member which can be controlled to assume any of a number of curved shapes as in the performance of automated operations. The arm functions somewhat like the body of a snake or an elephant's trunk. The skeletal frame defines a plurality of similar elemental segments disclosed in the form of disc-like structures as well as turns in a helical loading configuration. The helical form includes interleaved flexible helix members interconnected in a chain-link form. Displacement of sections in the arm is accomplished by the action of two separate mechanisms. A deflection mechanism provides power to flex or curve an arm section while a distribution mechanism distributes the curvature along the length of the arm to seek a smooth, circular curve. Illustrative embodiments use hydraulic actuators integral with the frame; however, equivalents are disclosed. The resulting arm is a highly repetitive, mechanical structure.
摘要翻译：公开了一种灵活的机器人臂结构，其利用细长的骨架构件，其可以被控制为呈现自动化操作中的多个弯曲形状中的任何一个。手臂的功能有点像蛇或大象的躯干。骨架框架限定了以盘状结构的形式公开的多个类似的元件段以及以螺旋形加载构型的转弯。螺旋形式包括以链式形式互连的交错的柔性螺旋构件。手臂中的部位的移位是通过两个独立的机构的作用实现的。偏转机构提供弯曲或弯曲臂部分的能量，而分配机构沿着臂的长度分布曲率以寻求平滑的圆形曲线。示例性实施例使用与框架一体的液压致动器; 然而，公开了等同物。所得到的臂是高度重复的机械结构。

60. 发明授权

US4622992A Reaction control valve 失效
标题翻译：反应控制阀
公开(公告)号：US4622992A
公开(公告)日：1986-11-18
申请号：US458698
申请日：1983-01-17
申请人： Ivan E. Sutherland
发明人： Ivan E. Sutherland
IPC分类号： F16K11/07 , F16K39/04 , F16K31/12
CPC分类号： F16K11/0708 , F16K39/04 , Y10T137/2524 , Y10T137/2562 , Y10T137/2564 , Y10T137/7784 , Y10T137/7792
摘要： Forms of a reaction control valve are disclosed utilizing various control signals with linear and rotary displacement structures to balance flow reaction forces and attain desired signal-responsive positioning. Different flow passage configurations attain different degrees of damping. An embodiment of the valve functions as a flow proportioner.
摘要翻译：利用具有线性和旋转位移结构的各种控制信号来公开反应控制阀的形式，以平衡流动反作用力并获得期望的信号响应定位。不同的流道结构获得不同程度的阻尼。阀的一个实施例用作流量比较器。

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