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51. 发明申请

US20060113682A1 Semiconductor component having plate and stacked dice 有权
标题翻译：半导体元件具有板和堆叠的骰子
公开(公告)号：US20060113682A1
公开(公告)日：2006-06-01
申请号：US11333662
申请日：2006-01-17
申请人： Warren Farnworth , Alan Wood , William Hiatt , James Wark , David Hembree , Kyle Kirby , Pete Benson
发明人： Warren Farnworth , Alan Wood , William Hiatt , James Wark , David Hembree , Kyle Kirby , Pete Benson
IPC分类号： H01L23/48 , H01L23/52 , H01L23/04
CPC分类号： H01L21/561 , B33Y70/00 , B33Y80/00 , H01L21/563 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2221/68331 , H01L2224/02372 , H01L2224/0401 , H01L2224/05111 , H01L2224/05118 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05178 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05559 , H01L2224/05569 , H01L2224/05572 , H01L2224/05624 , H01L2224/05644 , H01L2224/05664 , H01L2224/05666 , H01L2224/13005 , H01L2224/13006 , H01L2224/13009 , H01L2224/13024 , H01L2224/13099 , H01L2224/16145 , H01L2224/73204 , H01L2224/97 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06582 , H01L2225/06596 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15312 , H01L2924/18161 , H01L2924/19015 , H01L2924/19041 , H01L2924/351 , H01L2924/207 , H01L2224/05552 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the base die. The component also includes an array of terminal contacts on the circuit side of the base die in electrical communication with the conductive vias. The component can also include an encapsulant on the back side of the base die, which substantially encapsulates the secondary die, and a polymer layer on the circuit side of the base die which functions as a protective layer, a rigidifying member and a stencil for forming the terminal contacts. A method for fabricating the component includes the step of bonding singulated secondary dice to base dice on a base wafer, or bonding a secondary wafer to the base wafer, or bonding singulated secondary dice to singulated base dice.
摘要翻译：半导体部件包括基模和层叠在基模上的二次模。基模具包括形成用于部件的内部信号传输系统的导电通孔，并允许二次管芯的电路侧接合到基座的后侧。该组件还包括与导电通孔电连通的基座芯片的电路侧上的端子触点阵列。该组件还可以包括在基模的背侧上的密封剂，其基本上封装次模，以及在用作保护层的基模的电路侧上的聚合物层，用于形成的用于固化的模板终端接触。一种用于制造该部件的方法包括将单个二次骰子接合到基底晶片上的基底骰子上，或将次晶片接合到基底晶片，或将单个二次骰子接合到单个基体骰子的步骤。

52. 发明授权

US06983536B2 Method and apparatus for manufacturing known good semiconductor die 失效
标题翻译：用于制造已知的良好半导体管芯的方法和装置
公开(公告)号：US06983536B2
公开(公告)日：2006-01-10
申请号：US10847969
申请日：2004-05-18
申请人： Warren Farnworth , Alan Wood
发明人： Warren Farnworth , Alan Wood
IPC分类号： H05K3/30
CPC分类号： H01L23/49838 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/06711 , G01R1/0735 , G01R3/00 , G01R31/2863 , G01R31/287 , G01R31/2889 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L24/80 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , Y10T29/49117 , Y10T29/49121 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , H01L2924/00 , H01L2224/05599
摘要： A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die. In the assembled carrier the die and interconnect are biased together by a force distribution mechanism that includes a bridge clamp, a pressure plate and a spring clip. Following testing of the die, the carrier is disassembled and the tested die is removed.
摘要翻译：提供了一种用于制造已知的良好半导体晶片的方法和装置。该方法包括以下步骤：测试包含在半导体晶片上的骰子的总功能; 锯切晶片以切割模具; 然后通过组装在具有适于建立管芯上的接合焊盘与外部测试电路之间的电连通的互连的载体中来测试管芯。用于载体的互连可以使用不同的接触技术形成，包括：刚性基板上的厚膜接触构件; 硅衬底上的自限制接触构件; 或具有纹理表面的微型块接触构件。在载体的组装期间，芯片和互连件被光学对准并且被放置成与预定的接触力接触。这就建立了互连上的接触构件和管芯的接合垫之间的电连接。在组装的载体中，管芯和互连件通过包括桥夹，压板和弹簧夹的力分配机构偏压在一起。在对模具进行测试之后，拆下载体并且移除被测试的模具。

53. 发明申请

US20050275084A1 Compliant contact pin assembly and card system 有权
标题翻译：符合接触针组件和卡片系统
公开(公告)号：US20050275084A1
公开(公告)日：2005-12-15
申请号：US11152513
申请日：2005-06-14
申请人： Kyle Kirby , Warren Farnworth , James Wark , William Hiatt , David Hembree , Alan Wood
发明人： Kyle Kirby , Warren Farnworth , James Wark , William Hiatt , David Hembree , Alan Wood
IPC分类号： G01R1/073 , H01L21/66 , H01L23/48 , H01L23/498 , H01L23/58 , H01R13/24 , H05K3/32 , H05K3/40 , H05K7/06 , H05K7/10
CPC分类号： G01R1/0735 , G01R1/07314 , H01L23/13 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2924/00014 , H01L2924/09701 , H01L2924/15311 , H01L2924/3511 , H01R12/714 , H01R13/24 , H01R2201/20 , H05K3/326 , H05K7/1069 , H05K2201/0314 , H05K2201/09036 , H05K2201/10378 , Y10T29/49165 , Y10T29/49174 , Y10T29/49204 , Y10T29/49222 , H01L2224/05599
摘要： A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material, and in another embodiment by compliantly flexible portions of the substrate.
摘要翻译：提供了柔性接触销组件和接触器卡系统。柔性接触销组件包括由基板的一部分形成的接触销，其中触头销顺从地保持通过柔性联接结构悬挂在基板内。衬底内的悬浮液导致与衬底的平面垂直的柔顺偏转。接触销组件通过使基板围绕接触销位置大体变薄而形成，然后特别地使基板在接触销位置周围特别地变薄以形成空隙。在一个实施例中，接触销被顺从地联接，在一个实施例中通过柔性耦合材料，并且在另一个实施例中，通过柔性柔性部分的衬底。

54. 发明申请

US20050275048A1 Microelectronic imagers and methods of packaging microelectronic imagers 有权
标题翻译：微电子成像器和包装微电子成像器的方法
公开(公告)号：US20050275048A1
公开(公告)日：2005-12-15
申请号：US10867352
申请日：2004-06-14
申请人： Warren Farnworth , Sidney Rigg , William Hiatt , Kyle Kirby , Peter Benson , James Wark , Alan Wood , David Hembree , Salman Akram , Charles Watkins
发明人： Warren Farnworth , Sidney Rigg , William Hiatt , Kyle Kirby , Peter Benson , James Wark , Alan Wood , David Hembree , Salman Akram , Charles Watkins
IPC分类号： H01L21/00 , H01L23/02 , H01L23/48 , H01L27/14 , H01L27/146 , H01L31/00 , H01L31/0203 , H01L31/0232
CPC分类号： H01L27/14618 , H01L23/481 , H01L24/48 , H01L31/0203 , H01L31/02325 , H01L2224/48227 , H01L2924/00014 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the die and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad with conductive fill material at least partially disposed in the passage. An electrically conductive support member is carried by and projects from the bond-pad. A cover over the image sensor is coupled to the support member.
摘要翻译：本文公开了微电子成像器和用于封装微电子成像器的方法。在一个实施例中，微电子成像单元可以包括微电子管芯，图像传感器，电耦合到图像传感器的集成电路以及电耦合到集成电路的接合焊盘。导电晶片互连延伸穿过管芯并且与焊盘接触。互连可以包括完全延伸穿过基底的通道和具有至少部分地设置在通道中的导电填充材料的接合垫。导电支撑构件由接合垫承载和突出。图像传感器上的盖连接到支撑构件。

55. 发明申请

US20050230825A1 Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer 失效
公开(公告)号：US20050230825A1
公开(公告)日：2005-10-20
申请号：US11083057
申请日：2005-03-16
申请人： Salman Akram , Alan Wood , Warren Farnworth
发明人： Salman Akram , Alan Wood , Warren Farnworth
IPC分类号： G01R1/04 , H01L21/60 , H01L23/13 , H01L23/48 , H01L23/498 , H05K3/32
CPC分类号： H01L23/13 , G01R1/0466 , G01R1/0483 , H01L23/49827 , H01L2224/05571 , H01L2224/05573 , H01L2224/131 , H01L2224/16237 , H01L2224/8114 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/15174 , H05K3/325 , H05K3/326 , H01L2224/05599
摘要： The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bumps formed thereon, a substrate having a plurality of contact pads distributed thereon and approximately aligned with the plurality of conductive bumps, and an anisotropically conductive layer disposed between and mechanically coupled to the bumped device and to the substrate. The anisotropically conductive layer electrically couples each of the conductive bumps with a corresponding one of the contact pads. In another embodiment, an apparatus for testing a bumped device having a plurality of conductive bumps includes a substrate having a plurality of contact pads distributed thereon and substantially alignable with the plurality of conductive bumps, and an anisotropically conductive layer disposed on the first surface and engageable with the plurality of conductive bumps to electrically couple each of the conductive bumps with a corresponding one of the contact pads. Alternately, the test apparatus may also include an alignment device or a bumped device handler. In another embodiment, a method of testing a bumped device includes engaging a plurality of contact pads with an anisotropically conductive layer, engaging the plurality of conductive bumps with the anisotropically conductive layer substantially opposite from and in approximate alignment with the plurality of contact pads, forming a plurality of conductive paths through the anisotropically conductive layer so that each of the conductive bumps is electrically coupled to one of the contact pads, and applying test signals through at least some of the contact pads and the conductive paths to at least some of the conductive bumps.

56. 发明申请

US20050194180A1 Compliant contact pin assembly, card system and methods thereof 失效
标题翻译：符合接触针组件，卡片系统及其方法
公开(公告)号：US20050194180A1
公开(公告)日：2005-09-08
申请号：US10791195
申请日：2004-03-02
申请人： Kyle Kirby , Warren Farnworth , James Wark , William Hiatt , David Hembree , Alan Wood
发明人： Kyle Kirby , Warren Farnworth , James Wark , William Hiatt , David Hembree , Alan Wood
IPC分类号： G01R1/073 , H01L21/66 , H01L23/48 , H01L23/498 , H01L23/58 , H01R13/24 , H05K3/32 , H05K3/40 , H05K7/06 , H05K7/10
CPC分类号： G01R1/0735 , G01R1/07314 , H01L23/13 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2924/00014 , H01L2924/09701 , H01L2924/15311 , H01L2924/3511 , H01R12/714 , H01R13/24 , H01R2201/20 , H05K3/326 , H05K7/1069 , H05K2201/0314 , H05K2201/09036 , H05K2201/10378 , Y10T29/49165 , Y10T29/49174 , Y10T29/49204 , Y10T29/49222 , H01L2224/05599
摘要： A compliant contact pin assembly, a contactor card, a testing system and methods for making and testing are provided. A compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material and in another embodiment by compliantly flexible portions of the substrate.
摘要翻译：提供了兼容的接触针组件，接触器卡，测试系统以及制造和测试方法。柔性接触销组件包括由衬底的一部分形成的接触针，其中触发销通过柔性耦合结构顺应地保持悬挂在衬底内。衬底内的悬浮液导致与衬底的平面垂直的柔顺偏转。接触销组件通过使基板围绕接触销位置大体变薄而形成，然后特别地使基板在接触销位置周围特别地变薄以形成空隙。在一个实施例中，接触销被顺从地联接，在一个实施例中通过柔性耦合材料并且在另一个实施例中通过柔性柔性部分的基底。

57. 发明申请

US20050101037A1 Test system with interconnect having conductive members and contacts on opposing sides 审中-公开
标题翻译：具有互连件的测试系统具有导电构件和在相对侧上的触点
公开(公告)号：US20050101037A1
公开(公告)日：2005-05-12
申请号：US10998269
申请日：2004-11-26
申请人： Warren Farnworth , Alan Wood , David Hembree
发明人： Warren Farnworth , Alan Wood , David Hembree
IPC分类号： H01L21/48 , H01L21/60 , H01L21/768 , H01L23/13 , H01L23/498 , H01L23/538 , H01L25/10 , H05K1/03 , H05K1/11 , H05K3/00 , H01L21/66 , G01R31/26
CPC分类号： H01L21/486 , H01L21/6835 , H01L21/76898 , H01L23/13 , H01L23/481 , H01L23/49827 , H01L23/5389 , H01L24/16 , H01L24/75 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/05569 , H01L2224/0557 , H01L2224/05573 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/16235 , H01L2224/73204 , H01L2224/75 , H01L2224/81801 , H01L2224/82039 , H01L2225/06513 , H01L2225/06541 , H01L2225/1005 , H01L2225/1058 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H05K1/0306 , H05K1/112 , H05K3/0029 , H05K3/0032 , H05K2201/09472 , H05K2201/0959 , H05K2201/09827 , H05K2201/09845 , H05K2201/10674 , H05K2201/10734 , H01L2924/00
摘要： A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The conductive members include enlarged terminal portions that are covered with a non-oxidizing metal. The method can be used to fabricate stackable semiconductor packages having integrated circuits in electrical communication with the external contacts. The method can also be used to fabricate interconnects for electrically engaging packages, dice and wafers for testing or for constructing electronic assemblies.
摘要翻译：一种用于制造半导体部件和互连的方法包括以下步骤：提供诸如半导体管芯的衬底，通过穿过衬底的激光钻孔通孔在衬底的相对侧上形成外部触点，以及在通孔中形成导电构件。导电构件包括被非氧化金属覆盖的扩大端子部分。该方法可用于制造具有与外部触点电连通的集成电路的可堆叠半导体封装。该方法还可用于制造用于电接合封装，裸片和晶片用于测试或构建电子组件的互连。

58. 发明申请

US20050064679A1 Consolidatable composite materials, articles of manufacture formed therefrom, and fabrication methods 审中-公开
标题翻译：可固化复合材料，由其制成的制品及其制造方法
公开(公告)号：US20050064679A1
公开(公告)日：2005-03-24
申请号：US10928381
申请日：2004-08-27
申请人： Warren Farnworth , Alan Wood
发明人： Warren Farnworth , Alan Wood
IPC分类号： E21B43/02 , G03F7/00 , G03F7/004 , H01L21/30 , H01L21/46
CPC分类号： G03F7/0037 , G03F7/0047
摘要： A composite material includes an unconsolidated, consolidatable component and a physical modifier component. The consolidatable component is configured to be selectively consolidated to form an article, while the physical modifier component provides desired physical properties. The physical modifier component may be an unconsolidated material dispersed throughout the consolidatable component or a preformed matrix including interstices within which the consolidatable component may be introduced. The consolidatable component of the composite material may be selectively consolidated to fix the at least one physical component therein. Alternatively, the consolidatable component may be nonselectively consolidated, then regions thereof selectively removed. Methods for fabricating articles from such composite materials are also disclosed, as are systems that are configured for use in fabricating articles from such composite materials.
摘要翻译：复合材料包括未固结的，可固结的组分和物理改性剂组分。可整合组件被配置为选择性地合并以形成物品，而物理修饰剂组分提供期望的物理性质。物理改性剂组分可以是分散在整个可整合组分中的未固结的材料或预先形成的基质，其中可以引入可固结组分的间隙。可以选择性地将复合材料的可固结部件固结以固定其中的至少一种物理组分。或者，可固化组分可以非选择性地固结，然后其区域被选择性地去除。还公开了从这种复合材料制造制品的方法，以及被配置用于从这种复合材料制造制品的系统。

59. 发明申请

US20050253619A1 Method for testing using a universal wafer carrier for wafer level die burn-in 失效
公开(公告)号：US20050253619A1
公开(公告)日：2005-11-17
申请号：US11172326
申请日：2005-06-30
申请人： Alan Wood , Tim Corbett
发明人： Alan Wood , Tim Corbett
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/26 , G01R31/28 , H01L21/60 , H01L21/66 , H01L23/13 , H05K3/00 , H05K3/40 , H05K3/42
CPC分类号： H01L24/80 , G01R1/0466 , G01R1/0483 , G01R1/0491 , G01R1/0735 , G01R3/00 , G01R31/2831 , G01R31/2855 , G01R31/2863 , G01R31/2867 , G01R31/2886 , G01R31/2889 , G01R31/2893 , H01L22/20 , H01L22/22 , H01L23/13 , H01L2224/16145 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/15151 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723
摘要： A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

60. 发明申请

US20050237076A1 Method for testing using a universal wafer carrier for wafer level die burn-in 失效
公开(公告)号：US20050237076A1
公开(公告)日：2005-10-27
申请号：US11170901
申请日：2005-06-30
申请人： Alan Wood , Tim Corbett
发明人： Alan Wood , Tim Corbett
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/26 , G01R31/28 , H01L21/60 , H01L21/66 , H01L23/13 , H05K3/00 , H05K3/40 , H05K3/42
CPC分类号： H01L24/80 , G01R1/0466 , G01R1/0483 , G01R1/0491 , G01R1/0735 , G01R3/00 , G01R31/2831 , G01R31/2855 , G01R31/2863 , G01R31/2867 , G01R31/2886 , G01R31/2889 , G01R31/2893 , H01L22/20 , H01L22/22 , H01L23/13 , H01L2224/16145 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/15151 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723
摘要： A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

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