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51. 发明授权

US06255833B1 Method for testing semiconductor dice and chip scale packages 失效
标题翻译：半导体芯片和芯片级封装的测试方法
公开(公告)号：US06255833B1
公开(公告)日：2001-07-03
申请号：US09098594
申请日：1998-06-17
申请人： Salman Akram , Alan G. Wood , David R. Hembree , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , David R. Hembree , Warren M. Farnworth
IPC分类号： G01R3102
CPC分类号： G01R1/0483 , H01L2224/48091 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/30107 , H01L2924/00014
摘要： A method and carrier for testing semiconductor dice such as bare dice or chip scale packages are provided. The carrier includes a base for retaining a single die, an interconnect for establishing temporary electrical communication with the die, and a force applying mechanism for biasing the die and interconnect together. In an illustrative embodiment the base includes conductors arranged in a universal pattern adapted to electrically connect to different sized interconnects. Interconnects are thus interchangeable on a base for testing different types of dice using the same base. The conductors on the base can be formed on a planar active surface of the base or on a stepped active surface having different sized cavities for mounting different sized interconnects. In an alternate embodiment the carrier includes an interposer. In a first interposer embodiment, the interposer connects directly to external test circuitry and can be changed to accommodate different sized interconnects. In a second interposer embodiment, the interposer connects to conductors on the base and adapts the base for use with different sized interconnects.
摘要翻译：提供了用于测试半导体裸片（例如裸裸片或芯片级封装）的方法和载体。载体包括用于保持单个管芯的基座，用于建立与管芯的临时电连通的互连件，以及用于偏压管芯并互连在一起的施力机构。在说明性实施例中，底座包括以适于电连接到不同尺寸的互连件的通用图案布置的导体。因此，互连在基座上可以互换，用于使用相同的基底测试不同类型的骰子。基座上的导体可以形成在基座的平面有源表面上或具有不同尺寸的空腔的阶梯式有源表面上，用于安装不同尺寸的互连。在替代实施例中，载体包括插入器。在第一插入器实施例中，插入器直接连接到外部测试电路，并且可以改变以适应不同尺寸的互连。在第二插入器实施例中，插入器连接到基座上的导体，并使基座适配于不同大小的互连使用。

52. 发明授权

US6100175A Method and apparatus for aligning and attaching balls to a substrate 有权
公开(公告)号：US6100175A
公开(公告)日：2000-08-08
申请号：US143631
申请日：1998-08-28
申请人： Alan G. Wood , Salman Akram , Mike Hess , David R. Hembree
发明人： Alan G. Wood , Salman Akram , Mike Hess , David R. Hembree
IPC分类号： H01L21/48 , H05K3/34 , H01L21/44
CPC分类号： H05K3/3478 , H01L21/4853 , H01L24/742 , H01L2224/11003 , H01L2224/11334 , H01L2224/4824 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H05K2203/041 , H05K2203/082 , Y10S438/975
摘要： A method for aligning and bonding balls to substrates, such as semiconductor wafers, dice and packages, is provided. The method employs a ball retaining plate having a pattern of micromachined cavities and vacuum conduits for retaining the balls. In addition, a substrate alignment member attached to the ball retaining plate, aligns the substrate to the balls. Using the substrate alignment member, bonding sites on the substrate can be placed in physical contact with the balls which are held by vacuum on the ball retaining plate. Next, the ball alignment plate and substrate can be place in a furnace for reflowing and bonding the balls to the bonding sites. An apparatus for performing the method includes the ball retaining plate and the substrate alignment member. A system for performing the method includes a ball loader mechanism for loading balls onto the ball retaining plate, and a vacuum fixture for applying a vacuum to the ball retaining cavities.

53. 发明授权

US6064216A Apparatus for testing semiconductor wafers 有权
标题翻译：半导体晶片测试装置
公开(公告)号：US6064216A
公开(公告)日：2000-05-16
申请号：US241553
申请日：1999-02-01
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood , David R. Hembree , James M. Wark , John O. Jacobson
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood , David R. Hembree , James M. Wark , John O. Jacobson
IPC分类号： G01R1/04 , G01R31/28 , G01R31/02
CPC分类号： G01R1/0491 , G01R31/2886
摘要： A method, apparatus and system for testing semiconductor wafers are provided. The method includes providing a wafer carrier to provide an electrical path for receiving and transmitting test signals to the wafer. The wafer carrier includes a base for retaining the wafer, and an interconnect having contact members configured to establish electrical communication with contact locations on the wafer. The wafer carrier can include one or more compressible spring members configured to bias the wafer and interconnect together in the assembled carrier. The wafer carrier can be assembled, with the wafer in alignment with the interconnect, using optical alignment techniques, and an assembly tool similar to aligner bonder tools used for flip chip bonding semiconductor dice. A system for use with the carrier can include a testing apparatus configured to apply test signals through the carrier to the wafer while the wafer is subjected to temperature cycling.
摘要翻译：提供了一种用于测试半导体晶片的方法，装置和系统。该方法包括提供晶片载体以提供用于接收和传输测试信号到晶片的电路径。晶片载体包括用于保持晶片的基座和具有被配置为与晶片上的接触位置建立电连通的接触构件的互连。晶片载体可以包括被配置为偏置晶片并在组装的载体中互连在一起的一个或多个可压缩弹簧构件。可以使用光学对准技术来组装晶片载体，其中晶片与互连对准，以及类似于用于倒装芯片接合半导体晶片的对准器焊接工具的组装工具。与载体一起使用的系统可以包括测试装置，其被配置为在晶片受到温度循环的同时将测试信号通过载体施加到晶片。

54. 发明授权

US5955877A Method and apparatus for automatically positioning electronic dice within component packages 有权
标题翻译：电子管芯在组件封装内自动定位的方法和装置
公开(公告)号：US5955877A
公开(公告)日：1999-09-21
申请号：US170844
申请日：1998-10-13
申请人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
发明人： Warren M. Farnworth , Alan G. Wood , John O. Jacobson , David R. Hembree , James M. Wark , Jennifer L. Folaron , Robert J. Folaron , Jay C. Nelson , Lelan D. Warren
IPC分类号： G01R31/26 , G01R31/28 , G01R31/311 , H01L21/00 , H01L21/60 , H01L21/66 , H01L21/68 , H05K13/08
CPC分类号： H01L21/67276 , G01R31/2851 , G01R31/2886 , G01R31/2893 , H01L21/67126 , H01L21/67242 , H01L21/67259 , H01L21/681 , H01L24/74 , H05K13/08 , G01R31/311 , H01L2924/12042 , H01L2924/14 , Y10T29/49004 , Y10T29/49131 , Y10T29/53174 , Y10T29/53178
摘要： A method and apparatus of assembling and disassembling semiconductor dice to be tested from the components of a temporary test package. A computer-controlled vision system is employed to align the dice with the temporary test package bases, and an automated robot arm system is employed to retrieve and assemble the dice with the various package components. The invention has particular utility in the burn-in and other pre-packaging testing of dice to establish known good dice (KGD).
摘要翻译：从临时测试包的组件组装和拆卸要测试的半导体骰子的方法和装置。采用计算机控制的视觉系统将骰子与临时测试包基座对准，并且采用自动机器人手臂系统来检索和组装骰子与各种包装部件。本发明在骰子的老化和其他预包装测试中具有特殊的用途，以建立已知的骰子（KGD）。

55. 发明授权

US5915977A System and interconnect for making temporary electrical connections with bumped semiconductor components 有权
标题翻译：用于与凸起的半导体部件进行临时电连接的系统和互连
公开(公告)号：US5915977A
公开(公告)日：1999-06-29
申请号：US138612
申请日：1998-08-24
申请人： David R. Hembree , John O. Jacobson , James M. Wark , Warren M. Farnworth , Salman Akram , Alan G. Wood
发明人： David R. Hembree , John O. Jacobson , James M. Wark , Warren M. Farnworth , Salman Akram , Alan G. Wood
IPC分类号： G01R1/04 , H01L21/00 , H01R12/04 , H05K3/32 , H01R9/09
CPC分类号： H01L21/67144 , G01R1/0408 , H05K3/326 , H01L2224/1601 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2224/81385
摘要： An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.
摘要翻译：提供了一种用于与具有接触凸块的半导体部件建立临时电连通的互连和系统。互连包括具有适于电接触接触凸块的接触部件图案的基板。衬底可由诸如陶瓷，硅，FR-4或光刻化学可加工玻璃的材料形成。接触构件可以形成为覆盖有与衬底上的导体和端子触点电连通的导电层的凹陷。或者，接触构件可以形成为适于穿透接触凸块的突起，作为具有粗糙纹理表面的微胶囊，或者形成为具有凹陷的沉积层。互连可以用于晶片级测试系统中，用于测试包含在晶片上的骰子，或者用于测试裸露的骰子或凸起的芯片级封装的芯片级测试系统。

56. 发明授权

US5541525A Carrier for testing an unpackaged semiconductor die 失效
标题翻译：用于测试未封装半导体芯片的载体
公开(公告)号：US5541525A
公开(公告)日：1996-07-30
申请号：US345064
申请日：1994-11-14
申请人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
发明人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42 , G01R31/02
CPC分类号： G01R1/0466 , G01R1/0483 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/75 , H01L24/80 , H01L24/85 , H05K3/4007 , G01R3/00 , G01R31/2863 , H01L2224/16145 , H01L2224/48 , H01L2224/75 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/09701 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423
摘要： A carrier for testing an unpackaged semiconductor die is provided. The carrier includes: a base; a temporary interconnect for establishing electrical communication between the die and external test circuitry; a retention mechanism for securing the interconnect to the base; and a force distribution mechanism for biasing the die and interconnect together. The interconnect includes a substrate having raised contact members adapted to penetrate bond pads, or tests pads, on the die to form an electrical connection. Conductive traces are formed on the substrate in electrical communication with the raised contact members and connect to external connectors formed on the base. The interconnect is adapted for testing a particular type of die but is interchangeable with other interconnects to permit testing of different types of dice using a universal carrier.
摘要翻译：提供了用于测试未封装的半导体管芯的载体。承运人包括：基地; 用于建立管芯和外部测试电路之间的电通信的临时互连; 用于将互连件固定到基座的保持机构; 以及用于偏压模具并互连在一起的力分配机构。互连包括具有凸起的接触构件的衬底，该衬底适于穿过模具上的接合焊盘或测试衬垫以形成电连接。导电迹线形成在与凸起接触构件电连通的基板上，并连接到形成在基座上的外部连接器。互连适用于测试特定类型的管芯，但可与其他互连互换，以允许使用通用载体测试不同类型的管芯。

57. 发明申请

US20120043670A1 Semiconductor Module System Having Stacked Components With Encapsulated Through Wire Interconnects (TWI) 有权
标题翻译：半导体模块系统具有封装的通过线互连的堆叠元件（TWI）
公开(公告)号：US20120043670A1
公开(公告)日：2012-02-23
申请号：US13285490
申请日：2011-10-31
申请人： David R. Hembree , Alan G. Wood
发明人： David R. Hembree , Alan G. Wood
IPC分类号： H01L25/00 , H01L21/60 , H01L21/58
CPC分类号： H01L24/16 , G01R1/06716 , G01R1/07307 , H01L21/486 , H01L21/565 , H01L21/568 , H01L21/76877 , H01L21/76885 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/81 , H01L24/85 , H01L25/0657 , H01L25/105 , H01L2224/02125 , H01L2224/0233 , H01L2224/02333 , H01L2224/02335 , H01L2224/02372 , H01L2224/02373 , H01L2224/02375 , H01L2224/0333 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05548 , H01L2224/05552 , H01L2224/05554 , H01L2224/05555 , H01L2224/05567 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/1134 , H01L2224/13009 , H01L2224/13024 , H01L2224/13082 , H01L2224/131 , H01L2224/16146 , H01L2224/45014 , H01L2224/45015 , H01L2224/451 , H01L2224/45116 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45572 , H01L2224/45639 , H01L2224/45644 , H01L2224/45655 , H01L2224/45684 , H01L2224/45698 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48455 , H01L2224/48463 , H01L2224/4847 , H01L2224/48471 , H01L2224/48475 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/4899 , H01L2224/48992 , H01L2224/78301 , H01L2224/85051 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85951 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/1058 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/07811 , H01L2924/10155 , H01L2924/10161 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/181 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30105 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2224/45164 , H01L2924/013 , H01L2924/00013
摘要： A semiconductor module system includes a module substrate and first and second semiconductor components stacked on the module substrate. The stacked semiconductor components include through wire interconnects that form an internal signal transmission system for the module system. Each through wire interconnect includes a via, a wire in the via and first and second contacts on the wire.
摘要翻译：半导体模块系统包括模块基板和堆叠在模块基板上的第一和第二半导体部件。层叠的半导体部件包括形成用于模块系统的内部信号传输系统的通线互连。每个通线互连包括通孔，通孔中的导线以及导线上的第一和第二触点。

58. 发明授权

US07883908B2 Method for fabricating semiconductor component having encapsulated through wire interconnect (TWI) 有权
标题翻译：用于制造通过导线互连（TWI）封装的半导体部件的方法
公开(公告)号：US07883908B2
公开(公告)日：2011-02-08
申请号：US12581255
申请日：2009-10-19
申请人： David R. Hembree , Alan G. Wood
发明人： David R. Hembree , Alan G. Wood
IPC分类号： H01L21/60
CPC分类号： H01L24/16 , G01R1/06716 , G01R1/07307 , H01L21/486 , H01L21/565 , H01L21/568 , H01L21/76877 , H01L21/76885 , H01L21/76898 , H01L23/481 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/81 , H01L24/85 , H01L25/0657 , H01L25/105 , H01L2224/02125 , H01L2224/0233 , H01L2224/02333 , H01L2224/02335 , H01L2224/02372 , H01L2224/02373 , H01L2224/02375 , H01L2224/0333 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05548 , H01L2224/05552 , H01L2224/05554 , H01L2224/05555 , H01L2224/05567 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/1134 , H01L2224/13009 , H01L2224/13024 , H01L2224/13082 , H01L2224/131 , H01L2224/16146 , H01L2224/45014 , H01L2224/45015 , H01L2224/451 , H01L2224/45116 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45572 , H01L2224/45639 , H01L2224/45644 , H01L2224/45655 , H01L2224/45684 , H01L2224/45698 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48455 , H01L2224/48463 , H01L2224/4847 , H01L2224/48471 , H01L2224/48475 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/4899 , H01L2224/48992 , H01L2224/78301 , H01L2224/85051 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85951 , H01L2225/06506 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2225/1058 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/07811 , H01L2924/10155 , H01L2924/10161 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/181 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30105 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2224/45164 , H01L2924/013 , H01L2924/00013
摘要： A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.
摘要翻译：一种用封装的直通线互连制造半导体部件的方法包括以下步骤：提供具有第一面，第二面和基板接触的基板; 在基板接触中形成通孔，将基板形成到第二面; 将电线放在通孔中; 在靠近第一侧的导线上形成第一触点，并且在靠近第二侧的导线上形成第二触点; 并在第一侧上形成聚合物层，留下暴露的第一接触。聚合物层可以使用薄膜辅助成型方法形成，包括以下步骤：在粘合部件的顶端部分上形成模具膜，模制聚合物层，然后移除模具膜以暴露粘合部件的末端部分。通线互连提供了在半导体衬底的相对侧上具有触点的多电平互连。

59. 发明授权

US07723741B2 Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers 有权
标题翻译：用于封装的微电子成像器的间隔器以及制造和使用间隔件用于成像器的晶片级封装的方法
公开(公告)号：US07723741B2
公开(公告)日：2010-05-25
申请号：US11451398
申请日：2006-06-13
申请人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Rickie C. Lake
发明人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Rickie C. Lake
IPC分类号： H01L21/00
CPC分类号： H01L31/0203 , H01L27/14618 , H01L27/14625 , H01L27/14634 , H01L27/14683 , H01L2224/48227 , H01L2224/48091 , H01L2924/00014
摘要： Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can propagate. The imager dies include image sensors and integrated circuitry coupled to the image sensors. The method further includes providing a spacer having a web that includes an adhesive and has openings arranged to be aligned with the image sensors. For example, the web can be a film having an adhesive coating, or the web itself can be a layer of adhesive. The method continues by assembling the imager workpiece with the cover substrate such that (a) the spacer is between the imager workpiece and the cover substrate, and (b) the openings are aligned with the image sensors. The attached web is not cured after the imager workpiece and the cover substrate have both been adhered to the web. As such, the web does not outgas contaminants into the compartments in which the image sensors are housed.
摘要翻译：包装微电子成像仪和封装的微电子成像仪的方法。这种方法的实施例可以包括提供具有以模片图案布置的多个成像模具的成像工件，并提供覆盖基板，期望的辐射可以通过该基板传播。成像器裸片包括耦合到图像传感器的图像传感器和集成电路。该方法还包括提供具有包括粘合剂并具有布置成与图像传感器对准的开口的腹板的间隔件。例如，网可以是具有粘合剂涂层的膜，或者网本身可以是一层粘合剂。该方法通过将成像器工件与盖基板组装成使得（a）间隔件位于成像器工件和盖基板之间，并且（b）开口与图像传感器对准，该方法继续。在成像器工件和盖基板都已经粘附在卷材上之后，连接的卷材不固化。因此，纸幅不会将污染物排出到其中容纳图像传感器的隔室中。

60. 发明授权

US07589010B2 Semiconductor devices with permanent polymer stencil and method for manufacturing the same 有权
标题翻译：具有永久聚合物模板的半导体器件及其制造方法
公开(公告)号：US07589010B2
公开(公告)日：2009-09-15
申请号：US11210606
申请日：2005-08-23
申请人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Syed Sajid Ahmad , Michael E. Hess , John O. Jacobson
发明人： Warren M. Farnworth , Alan G. Wood , James M. Wark , David R. Hembree , Syed Sajid Ahmad , Michael E. Hess , John O. Jacobson
IPC分类号： H01L21/44
CPC分类号： H01L23/544 , B33Y30/00 , B33Y80/00 , H01L21/563 , H01L23/293 , H01L23/3157 , H01L24/81 , H01L24/83 , H01L2223/5448 , H01L2224/05571 , H01L2224/05573 , H01L2224/11005 , H01L2224/1147 , H01L2224/11472 , H01L2224/16 , H01L2224/293 , H01L2224/81011 , H01L2224/8121 , H01L2224/81815 , H01L2224/83851 , H01L2924/00014 , H01L2924/01078 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/3512 , H01L2924/00 , H01L2224/05599
摘要： Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices.
摘要翻译：使用具有孔的永久或临时聚合物层来制造半导体器件的方法来暴露接触焊盘并覆盖半导体器件的有源表面。

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