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    • 59. 发明申请
    • Transistor including flatband voltage control through interface dipole engineering
    • 晶体管包括通过接口偶极工程的平带电压控制
    • US20070158702A1
    • 2007-07-12
    • US11322827
    • 2005-12-30
    • Mark DoczyMatthew MetzJustin BraskRobert ChauGilbert Dewey
    • Mark DoczyMatthew MetzJustin BraskRobert ChauGilbert Dewey
    • H01L29/76H01L29/94H01L31/00
    • H01L29/785H01L29/4908
    • A transistor comprising a semiconductor including a source, a drain, and a channel interposed between the source and the drain; a first dielectric layer having a first thickness, the first dielectric layer being positioned on the channel; a second dielectric layer having a second thickness, the second dielectric layer being positioned on the first dielectric layer; and a gate electrode on the second dielectric layer, wherein the transistor gate is made of a mid-gap metal. A process comprising depositing a first dielectric layer on at least one surface of a semiconductor layer; depositing a second dielectric layer on the first dielectric layer; depositing a layer of mid-gap metal on the second dielectric layer; and patterning and etching the first dielectric layer, the second dielectric layer and the layer of mid-gap metal to create a gate electrode separated from the substrate by a first dielectric and a second dielectric. Other embodiments are disclosed and claimed.
    • 一种晶体管,包括:半导体,包括源极,漏极和介于源极和漏极之间的沟道; 具有第一厚度的第一介电层,所述第一介电层位于所述通道上; 具有第二厚度的第二介电层,所述第二介电层位于所述第一介电层上; 以及第二介质层上的栅电极,其中晶体管栅极由中间间隙金属制成。 一种方法,包括在半导体层的至少一个表面上沉积第一介电层; 在所述第一电介质层上沉积第二电介质层; 在所述第二电介质层上沉积中间间隙金属层; 以及对第一电介质层,第二电介质层和中间间隙金属层进行图案化和蚀刻以产生通过第一电介质和第二电介质与衬底分离的栅电极。 公开和要求保护其他实施例。