专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US08201004B2 Entry/exit control to/from a low power state in a complex multi level memory system 有权
标题翻译：在复杂的多级存储器系统中进/出控制低功率状态
公开(公告)号：US08201004B2
公开(公告)日：2012-06-12
申请号：US11855602
申请日：2007-09-14
申请人： Timothy David Anderson , Lewis Nardini , Jose Luis Flores , Abhijeet Chachad , Raguram Damodaran , Joseph R. M. Zbiciak , Gary Swoboda
发明人： Timothy David Anderson , Lewis Nardini , Jose Luis Flores , Abhijeet Chachad , Raguram Damodaran , Joseph R. M. Zbiciak , Gary Swoboda
IPC分类号： G06F1/04 , G06F1/10 , G06F1/18 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.
摘要翻译：嵌入式巨型模块和嵌入式CPU通过硬件和软件的组合实现节能。 CPU在兆模块内配置掉电控制器（PDC）逻辑，并且可以在处理器空闲周期期间软件触发逻辑模块的低功耗状态。要从此掉电状态唤醒，系统事件将通过模块中断控制器发送到CPU。因此，进入低功耗状态是在非活动期间进行软件驱动，并且电源恢复是需要CPU注意的系统活动。

52. 发明授权

US07805644B2 Multiple pBIST controllers 有权
标题翻译：多个pBIST控制器
公开(公告)号：US07805644B2
公开(公告)日：2010-09-28
申请号：US11967148
申请日：2007-12-29
申请人： Raguram Damodaran , Umang Bharatkumar Thakkar , John David Sayre
发明人： Raguram Damodaran , Umang Bharatkumar Thakkar , John David Sayre
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G06F11/27
摘要： A system on a single integrated circuit chip (SoC) includes a plurality of operational circuits to be tested. A plurality of programmable built-in self-test (pBIST) controllers is connected to respective ones of the plurality of operational circuits in a manner that allows the pBIST controllers to test the respective operation circuits in parallel. An interface is connected to each of the plurality of pBIST controllers for connection to an external tester to facilitate programming of each of the plurality of pBIST controllers by the external tester, such that the plurality of pBIST controllers are operable to test the plurality of operational circuits in parallel and report the results of the parallel tests to the external tester, thereby reducing test time.
摘要翻译：单个集成电路芯片（SoC）上的系统包括要测试的多个操作电路。多个可编程内置自检（pBIST）控制器以允许pBIST控制器并行测试各个操作电路的方式连接到多个操作电路中的相应的一个操作电路。接口连接到多个pBIST控制器中的每一个，用于连接到外部测试器，以便外部测试器对多个pBIST控制器中的每一个进行编程，使得多个pBIST控制器可操作以测试多个操作电路并行并行测试结果报告给外部测试仪，从而减少测试时间。

53. 发明授权

US07487421B2 Emulation cache access for tag view reads 有权
标题翻译：标签视图读取的仿真缓存访问
公开(公告)号：US07487421B2
公开(公告)日：2009-02-03
申请号：US11422740
申请日：2006-06-07
申请人： Raguram Damodaran , Ananthakrishnan Ramamurti
发明人： Raguram Damodaran , Ananthakrishnan Ramamurti
IPC分类号： G01R31/28
CPC分类号： G01R31/3187
摘要： A built-in self test unit reads tag bits of a predetermined cache entry and outputs these tag bits via an external interface. The built-in self test unit enters an emulation mode upon receipt of an emulation signal via the external interface when a first configuration register has a predetermined state. The built-in self test unit then reads tag bits upon each memory mapped read of a second configuration register. The read operation advances to next sequential tag bits upon each memory mapped read of the second configuration register. The tag bits include at least one valid bit and at least one dirty bit. The tag bits also include the most significant bits of the cached address.
摘要翻译：内置自检单元读取预定高速缓存条目的标签位，并通过外部接口输出这些标签位。当第一配置寄存器具有预定状态时，内置自检单元在经由外部接口接收到仿真信号时进入仿真模式。内置的自检单元然后在第二个配置寄存器的每个存储器映射读取时读取标签位。在第二配置寄存器的每次存储器映射读取时，读操作进行到下一个顺序标签位。标签位包括至少一个有效位和至少一个脏位。标记位还包括缓存地址的最高有效位。

54. 发明授权

US07475313B2 Unique pBIST features for advanced memory testing 有权
标题翻译：独特的pBIST功能，用于高级内存测试
公开(公告)号：US07475313B2
公开(公告)日：2009-01-06
申请号：US11422732
申请日：2006-06-07
申请人： Raguram Damodaran , Ananthakrishnan Ramamurti
发明人： Raguram Damodaran , Ananthakrishnan Ramamurti
IPC分类号： G01R31/28
CPC分类号： G06F11/273 , G01R31/3187
摘要： This invention is new built-in self test instructions. A pointer register stores data identifying one bit of a data register. That bit determines whether the data of another data register is used in test in native form or in inverted form. Different built-in self test instructions update pointer including reset to the first bit, no change, increment to the next bit and decrement to the previous bit. For write instructions the selected normal or inverted data is written into memory. For read instructions the selected normal or inverted data is compared with data read from a memory.
摘要翻译：本发明是新的内置自检指令。指针寄存器存储识别数据寄存器的一位的数据。该位确定另一数据寄存器的数据是以本机形式还是以倒置形式用于测试。不同的内置自检指令更新指针，包括复位到第一位，无变化，递增到下一位，并递减到前一位。对于写指令，所选的正常或反相数据被写入存储器。对于读取指令，将所选择的正常或反相数据与从存储器读取的数据进行比较。

55. 发明申请

US20070033471A1 Hardware Configuration of pBIST 审中-公开
标题翻译： pBIST的硬件配置
公开(公告)号：US20070033471A1
公开(公告)日：2007-02-08
申请号：US11422743
申请日：2006-06-07
申请人： Raguram Damodaran , Ananthakrishnan Ramamurti , Umang Thakkur
发明人： Raguram Damodaran , Ananthakrishnan Ramamurti , Umang Thakkur
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G06F11/27
摘要： This invention is a method of constructing an integrated circuit with built-in self test. The built-in self test includes a built-in self test unit a read only memory storing test algorithms and test data. The built-in self test unit of a particular integrated circuit includes a subset of all test circuits for inclusion for testing a universe of possible operational circuits. The selected subset corresponds to operational circuits of the current integrated circuit.
摘要翻译：本发明是构建具有内置自检的集成电路的方法。内置的自检包括一个内置的自检单元，存储测试算法和测试数据的只读存储器。特定集成电路的内置自检单元包括用于测试可能的运行电路的宇宙的所有测试电路的子集。所选择的子集对应于当前集成电路的运行电路。

56. 发明申请

US20070033469A1 ROM-Based Memory Testing 有权
标题翻译：基于ROM的内存测试
公开(公告)号：US20070033469A1
公开(公告)日：2007-02-08
申请号：US11422726
申请日：2006-06-07
申请人： Ananthakrishnan Ramamurti , Raguram Damodaran
发明人： Ananthakrishnan Ramamurti , Raguram Damodaran
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C17/14
摘要： This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data only for each test set stored in the pBIST ROM into read/write registers. These registers are memory mapped readable/writable. A configuration register has an algorithm bit and a data bit which determines whether the corresponding algorithm or data is loaded from the pBIST ROM. The pBIST unit includes another configuration register having one bit corresponding to each possible test set stored in the pBIST ROM. The pBIST unit runs a test set if the corresponding bit in the configuration register has a first digital state.
摘要翻译：本发明独特地划分用于存储程序和数据信息的pBIST ROM。 pBIST单元选择性地将存储在pBIST ROM中的每个测试集合的算法和数据，仅算法或数据加载到读/写寄存器中。这些寄存器是可读写的内存映射。配置寄存器具有算法位和数据位，用于确定对应的算法或数据是否从pBIST ROM加载。 pBIST单元包括具有与存储在pBIST ROM中的每个可能测试集相对应的一个位的另一个配置寄存器。如果配置寄存器中的相应位具有第一数字状态，则pBIST单元运行测试集。

57. 发明授权

US08904249B2 At speed testing of high performance memories with a multi-port BIS engine 有权
标题翻译：在使用多端口BIS引擎的高性能存储器进行速度测试时
公开(公告)号：US08904249B2
公开(公告)日：2014-12-02
申请号：US13447193
申请日：2012-04-14
申请人： Raguram Damodaran , Naveen Bhoria
发明人： Raguram Damodaran , Naveen Bhoria
IPC分类号： G11C29/00
CPC分类号： G11C29/14 , G11C29/48 , G11C2029/0401
摘要： A programmable Built In Self Test (BIST) system used to test embedded memories where the memories may be operating at a clock frequency higher than the operating frequency of the BIST. A plurality of BIST memory ports are used to generate multiple memory test instructions in parallel, and the parallel instructions are then merged to generate a single memory test instruction stream at a speed that is a multiple of the BIST operating frequency.
摘要翻译：一个可编程内建自测（BIST）系统，用于测试嵌入式存储器，其中存储器可能以高于BIST的工作频率的时钟频率工作。多个BIST存储器端口用于并行地产生多个存储器测试指令，然后并行指令被合并以以BIST操作频率的倍数的速度生成单个存储器测试指令流。

58. 发明授权

US08862835B2 Multi-port register file with an input pipelined architecture and asynchronous read data forwarding 有权
标题翻译：具有输入流水线架构和异步读取数据转发的多端口寄存器文件
公开(公告)号：US08862835B2
公开(公告)日：2014-10-14
申请号：US13160156
申请日：2011-06-14
申请人： Raguram Damodaran , Ramakrishnan Vankatasubramanian , Naveen Bhoria
发明人： Raguram Damodaran , Ramakrishnan Vankatasubramanian , Naveen Bhoria
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F5/06 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30141 , G06F5/06 , G06F9/3826
摘要： In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. When the read address is identical to the write address stored in the pipelined memory, the result of a bit-wise ANDing of data stored in pipelined synchronous data registers and data stored in pipelined synchronous bit-wise registers is presented at the output of the multi-port register file.
摘要翻译：在本发明的一个实施例中，多端口寄存器文件包括流水线的写入端口输入（例如写入地址，写入使能，数据输入）以及不是流水线的同步和读出端口输入（例如，读取地址）。由于写入端口输入是流水线的，所以它们被存储在流水线寄存器中。当数据写入多端口寄存器文件时，数据将在第一个时钟周期内首先写入流水线寄存器。在下一个时钟周期，数据从流水线寄存器读取并写入存储器阵列寄存器。当读取地址与存储在流水线存储器中的写入地址相同时，存储在流水线同步数据寄存器中的数据的逐位AND运算结果和存储在流水线同步逐位寄存器中的数据显示在多路复用器的输出端 -port注册文件。

59. 发明申请

US20130275822A1 At Speed Testing of High Performance Memories with a Multi-Port BIS Engine 有权
标题翻译：在具有多端口BIS引擎的高性能存储器的速度测试中
公开(公告)号：US20130275822A1
公开(公告)日：2013-10-17
申请号：US13447193
申请日：2012-04-14
申请人： Raguram Damodaran , Naveen Bhoria
发明人： Raguram Damodaran , Naveen Bhoria
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/14 , G11C29/48 , G11C2029/0401
摘要： A programmable Built In Self Test (BIST) system used to test embedded memories where the memories may be operating at a clock frequency higher than the operating frequency of the BIST. A plurality of BIST memory ports are used to generate multiple memory test instructions in parallel, and the parallel instructions are then merged to generate a single memory test instruction stream at a speed that is a multiple of the BIST operating frequency.
摘要翻译：一个可编程内建自测（BIST）系统，用于测试嵌入式存储器，其中存储器可能以高于BIST的工作频率的时钟频率工作。多个BIST存储器端口用于并行地产生多个存储器测试指令，然后并行指令被合并以以BIST操作频率的倍数的速度生成单个存储器测试指令流。

60. 发明授权

US07603487B2 Hardware configurable hub interface unit 有权
标题翻译：硬件可配置的集线器接口单元
公开(公告)号：US07603487B2
公开(公告)日：2009-10-13
申请号：US11128680
申请日：2005-05-13
申请人： Shoban Srikrishna Jagathesan , Sanjive Agarwala , Raguram Damodaran
发明人： Shoban Srikrishna Jagathesan , Sanjive Agarwala , Raguram Damodaran
IPC分类号： G06F3/00 , G06F13/00 , G06F13/12
CPC分类号： G06F13/28 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A data transfer apparatus with hub and ports includes design configurable hub interface units (HIU) between the ports and corresponding external application units. The configurable HIU provides a single generic superset HIU that can be configured for specific more specialized applications during implementation as part of design synthesis. Configuration allows the super-set configurable HIU to be crafted into any one of several possible special purpose HIUs. This configuration is performed during the design phase and is not applied in field applications. Optimization aimed at eliminating functional blocks not needed in a specific design and simplifying and modifying other functional blocks allows for the efficient configuring of these other types of HIUs. Configuration of HIUs for specific needs can result in significant savings in silicon area and in power consumption.
摘要翻译：具有集线器和端口的数据传输装置包括在端口和相应的外部应用单元之间的设计可配置的集线器接口单元（HIU）。可配置的HIU提供单个通用超集HIU，可以在实现过程中为特定的更专门的应用程序配置，这是设计综合的一部分。配置允许将超级可配置HIU制作成几个可能的专用HIU中的任何一个。此配置在设计阶段执行，不适用于现场应用。旨在消除特定设计中不需要的功能块的优化，并简化和修改其他功能块允许有效配置这些其他类型的HIU。为特定需要配置HIU可以显着节省硅面积和功耗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式